Jerry A. Kreifels

A 90-ns one-million erase/program cycle 1-Mbit flash memory

Describes the design and performance of a 245-mil/sup 2/ 1-Mbit (128K*8) flash memory targeted for in-system reprogrammable applications. Developed from a 1.0- mu m EPROM-base technology, the 15.2- mu m/sup 2/ single-transistor EPROM tunnel oxide (ETOX) cell requires only 42 percent of the area required by the previous 1.5- mu m device. One of the most significant aspects of this 1-Mbit flash memory is the one-million erase/program cycle capability. The 1-Mbit memory exhibits 90-ns read access time while the reprogramming performance gives a 900-ms array erase time and a 10- mu s/byte programming rate. Ample erase and program margins through one-million erase/program cycles are guaranteed by the internal verify circuits. Column redundancy is implemented with the utilization of flash memory cells to store repaired addresses. >

An in-system reprogrammable 32 K*8 CMOS flash memory

The authors describe the design and performance of a 192-mil/sup 2/ 256 K (32 K*8) flash memory targeted for in-system reprogrammable applications. Developed from a 1.5 mu m EPROM base technology with a one-transistor 6*6- mu m/sup 2/ cell, the device electrically erases all cells in the array matrix in 200 ms and electrically programs at the rate of 100 mu s/byte typical. The read performance is equivalent to comparable-density CMOS EPROM devices with a chip-enable access time of 110 ns at 30-mA active current consumption. A command-port interface facilitates microprocessor-controlled reprogramming capability. Device reliability has been increased over byte-alterable EEPROMs by reducing the program power supply to 12 V. Cycling endurance experiments have demonstrated that the device is capable of more than 10000 erase/program cycles. >

A 1.8 V 128 Mb 125 MHz multi-level cell flash memory with flexible read while write

A 128 Mb flash memory with a two bit-per-cell design on a 0.13 /spl mu/m technology achieves a random access time of 55 ns and 125 MHz synchronous operation. The design incorporates a flexible multi-partition memory architecture which allows a program or erase operation to occur in one partition of the memory while bursting data out of another partition. The die is 27.3 mm/sup 2/ with a 0.154 /spl mu/m/sup 2/ cell size.

A 3.3 V 16 Mb flash memory with advanced write automation

The design of this flash memory is governed by the following considerations. Use of flash memory to store both data and code requires fast write with interruptible erase. Portable systems operate at 3.3 V to optimize battery life, while the desktop remains primarily a 5 V platform. This 16 Mb flash memory on a 0.6 /spl mu/m CMOS process operates with either 3.3 or 5 V supply. In the 3.3 V mode, a word line boost circuit is enabled, the input buffer trip points are modified, and the read path circuits are reconfigured for optimum performance. This memory uses the host computer 12 V supply to minimize flash media cost and maximize flash media performance. The device contains an advanced user interface that allows the host to queue up to three commands for execution by the write state machine, designed to allow erase to be interrupted so a program operation can be executed. Two 256B page buffers improve write performance and reduce host overhead. Wafer yields are improved by including redundant row pairs and columns.<<ETX>>