Rodolfo Z. Garcia-Lozano

Simple improvement stage for low voltage WTA and Rank Order circuits

A simple improvement to Lazzaros Winner Take All (WTA) circuit is introduced. It allows lowering the voltage supply requirements so that it can be functional in fine line CMOS technology. A low voltage Rank Order Filter is derived from the WTA using current starving techniques. Electrical measurements of a prototype in CMOS 0.5µm technology verify the operation of the WTA circuit with VDD = 1.5V. Simulations in PSpice show the functionality of a Rank Order Circuit using the same principle.

Fowler-Nordheim Tunneling Characterization on Poly1-Poly2 Capacitors for the Implementation of Analog Memories in CMOS 0.5 μm Technology

The experimental results of the Fowler-Nordheim characterization using poly1-poly2 capacitors on CMOS ON Semi 0.5 μm technology are presented. This characterization allows the development, design, and characterization of a new current-mode analog nonvolatile memory. Experimental results of the memory cell architecture are presented and demonstrate the usefulness of the proposed architecture.

Low Voltage Lazzaro's WTA with enhanced loop gain

An additional stage for a Low Voltage Lazzaros Winner Take All (WTA) circuit is introduced. It allows lowering the voltage supply requirements so that it can be functional in fine line CMOS technology. Electrical measurements of a prototype in CMOS 0.5µm technology verify the operation of the WTA circuit with VDD=1.5V. Simulations in PSpice and stability issues are presented as well.

A very compact CMOS class AB current mirror for low voltage applications

This paper presents a compact bidirectional current mirror suitable for low voltage applications. The idea is to use complementary transistors in subthreshold which are able to set a reduced bias current through the mirror. The circuit presents a class AB operation with a THD near to 1% at 1MHz. The bandwidth is above 10MHz as shown by simulations using Spectre with 0.5μm CMOS technology parameters.

Low complexity CMOS MIN circuit for low voltage applications

In this work, a new MIN circuit for low voltage applications is presented. The approach uses a new low output impedance configuration which allows working with low power supply requirements. The circuit was simulated in PSpice and a chip prototype was fabricated and tested using CMOS AMI 0.5µm N-well technology.