Jesus E. Molinar-Solis

A High-Swing, High-Speed CMOS WTA Using Differential Flipped Voltage Followers

A high-performance CMOS winner-take-all circuit based on the differential flipped voltage follower is introduced. Simulations demonstrate the potential of the circuit to operate at very high speed, with high precision even for close input values and with low supply voltages. Experimental verification of the circuit is provided in a 0.5-mum CMOS technology.

Class AB low-voltage CMOS Voltage Follower

A modification of the flipped voltage follower (FVF) that provides efficient Class-AB operation is presented. The modified circuit has the capability to source and sink large output currents and, compared to previous approaches, it is able to maintain the output node at a constant voltage with respect to the input. This is achieved with a very small increase in the power dissipation and very small additional devices. Simulation results of this structure verifying the proposed operation are provided.

Transient and DC approximate expressions for diode circuits

In general terms, it is not possible to establish symbolic explicit analytic expressions of the operating point and transient analysis for circuits containing diodes modelled using an exponential function. Therefore, this work propose replacing the diode for an equivalent circuit obtained by using a power series and a Taylor series consecutively. Finally, we present a symbolic solution for some circuits that include diodes; resulting for the best case: for DC analysis a relative error of 1E-11 and for transient analysis a relative error ≤ 5E-4.

Simple improvement stage for low voltage WTA and Rank Order circuits

A simple improvement to Lazzaros Winner Take All (WTA) circuit is introduced. It allows lowering the voltage supply requirements so that it can be functional in fine line CMOS technology. A low voltage Rank Order Filter is derived from the WTA using current starving techniques. Electrical measurements of a prototype in CMOS 0.5µm technology verify the operation of the WTA circuit with VDD = 1.5V. Simulations in PSpice show the functionality of a Rank Order Circuit using the same principle.

Electrical stress in CdS thin film transistors using HfO2 gate dielectric

During thin film transistor (TFT) operation, gate dielectric is under a bias stress condition. In this work, bias stress effect for CdS TFT using HfO2 as gate dielectric is analyzed. Threshold voltage, Ion/Ioff ratio, and subthreshold slope were studied in order to understand changes produced at the dielectric semiconductor interface. We observed that threshold voltage shift is related with negative charge trapping in the dielectric/semiconductor interface and for this phenomenon we propose a trapping charge model. Finally, the TFT output characteristic was modeled considering a shift in the threshold voltage for each gate voltage curve.

Programmable CMOS CNN Cell Based on Floating-gate Inverter Unit

At present, the Cellular Neural Network (CNN) is a potential parallel structure able to perform image processing tasks in real-time when is effectively implemented in CMOS technology. The CNN silicon integration success is due mainly to the local connectivity of processing cells. In this work, an alternative design based on floating-gate MOS inverters is presented, which uses unipolar signals for solving binary tasks. The approach brings a fast response in a reduced silicon area, as shown through electrical simulations. A prototype cell in CMOS technology (AMI, 1.2 micron) was fabricated and tested for eight image processing tasks.

Low-voltage differential voltage follower for WTA and fully differential applications

A low-voltage differential version of a high performance voltage follower is presented. The proposed circuit is very compact, and symmetric with respect to the input devices. Both differential input devices are enhanced by local shunt feedback, increasing the gain and, thus, reducing the output resistance for higher precision. The circuit has proved useful as a winner-take-all (WTA) circuit. It also features operation as a fully differential amplifier with low supply voltage requirements close to a transistors threshold voltage. Experimental results verifying the operation of the proposed structure are provided.

A novel divider using the Gilbert's cell with Floating Gate feedback

A very high frequency analog divider using Floating Gate transistors [1] is presented. The design is based on the Gilberts cell [2–3], which is formed by a four-quadrant multiplier, and operates in voltage mode where all the transistors are in the saturation region. Simulation results in 0.5um technology show that this cell is useful for high frequency applications.

Class AB flipped voltage follower with very low output resistance and no additional power

A modified version of the flipped voltage follower (FVF) with class AB operation and very low output resistance is presented. Instead of passing one of the large bidirectional output currents through the voltage following transistor, which considerably degrades the output resistance as in other variations, the proposed circuit maintains a constant current in this device and, hence, a very low output resistance. Complementary-type output transistors that depend on the same signal give the circuit the ability to provide large bidirectional currents at high frequency. The implementation only requires an additional resistor and one connection change, with no additional power consumption. Simulation and experimental results of the fabricated circuit in a 0.5 μm technology show an output resistance of the proposed circuit of 12Ω, with an enhancing factor of 60 with respect to previously reported variations.

Capacitance multiplier with large multiplication factor, high accuracy, and low power and silicon area for floating applications

A capacitance multiplier with high accuracy and reduced power consumption and silicon area, is presented. It offers a scaling factor based on ratios of resistors that can be physically matched to reduce deviations due to fabrication process. Resistor ratios also offer the property to define large scaling factors without increasing power consumption or silicon area. It is based on a modified current-mode multiplication technique that scales voltage magnitude instead of internal devices of the current-providing device. Simulation results show scaling factors of 10, 100, 1 k and 10 k. Experimental testing shows the results of the implementation of the floating equivalent multiplier implemented in a notch RLC filter with a scaling factor of 1 k.