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Featured researches published by Roger Gramunt.


IEEE Micro | 2016

Knights Landing: Second-Generation Intel Xeon Phi Product

Avinash Sodani; Roger Gramunt; Jesus Corbal; Ho-Seop Kim; Krishna N. Vinod; Sundaram Chinthamani; Steven R. Hutsell; Rajat Agarwal; Yen-Chen Liu

This article describes the architecture of Knights Landing, the second-generation Intel Xeon Phi product family, which targets high-performance computing and other highly parallel workloads. It provides a significant increase in scalar and vector performance and a big boost in memory bandwidth compared to the prior generation, called Knights Corner. Knights Landing is a self-booting, standard CPU that is completely binary compatible with prior Intel Xeon processors and is capable of running all legacy workloads unmodified. Its innovations include a core optimized for power efficiency, a 512-bit vector instruction set, a memory architecture comprising two types of memory for high bandwidth and large capacity, a high-bandwidth on-die interconnect, and an integrated on-package network fabric. These features enable the Knights Landing processor to provide significant performance improvement for computationally intensive and bandwidth-bound workloads while still providing good performance on unoptimized legacy workloads, without requiring any special way of programming other than the standard CPU programming model.


international symposium on computer architecture | 2002

Tarantula: a vector extension to the alpha architecture

Roger Espasa; Federico Ardanaz; Joel S. Emer; Stephen Felix; Julio Gago; Roger Gramunt; Isaac Hernandez; Toni Juan; Geoff Lowney; Matthew Mattina; André Seznec


Archive | 2009

Implementing Vector Memory Operations

Roger Espasa; Joel S. Emer; Geoff Lowney; Roger Gramunt; Santiago Galan; Toni Juan; Jesus Corbal; Federico Ardanaz; Isaac Hernandez


Archive | 2005

Technique for setting a vector mask

Roger Espasa; Roger Gramunt


Archive | 2007

METHOD, SYSTEM, AND APPARATUS FOR PAGE SIZING EXTENSION

Edward T. Grochowski; Julio Gago; Roger Gramunt; Roger Espasa; Rolf Kassa


Archive | 2010

Method, equipment, system and processor for setting a vector mask

Roger Espasa; Roger Gramunt


Archive | 2017

STATELESS CAPTURE OF DATA LINEAR ADDRESSES DURING PRECISE EVENT BASED SAMPLING

Roger Gramunt; Ramon Matas; Benjamin C. Chaffin; Neal S. Moyer; Rammohan Padmanabhan; Alexey P. Suprun; Matthew G. Smith


Archive | 2016

SCALABLE EVENT HANDLING IN MULTI-THREADED PROCESSOR CORES

Roger Gramunt; Rammohan Padmanabhan; Ramon Matas; Neal S. Moyer; Benjamin C. Chaffin; Avinash Sodani; Alexey P. Suprun; Vikram S. Sundaram; Chung-Lun Chan; Gerardo A. Fernandez; Julio Gago; Michael S. Yang; Aditya Kesiraju


Archive | 2016

METHOD AND APPARATUS FOR EFFICIENTLY MANAGING ARCHITECTURAL REGISTER STATE OF A PROCESSOR

Jesus Corbal; Dennis R. Bradford; Benjamin C. Chaffin; Taraneh Bahrami; Jonathan C. Hall; Thomas B. Maciukenas; Roger Gramunt; Rohan Sharma


Archive | 2015

METHOD AND APPARATUS FOR PERFORMING AN EFFICIENT SCATTER

Ramon Matas; Alexey P. Suprun; Roger Gramunt; Chung-Lun Chan; Rammohan Padmanabhan

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