Rola A. Baki

Distortion in RF CMOS short-channel low-noise amplifiers

An approach to estimate the distortion in CMOS short-channel (e.g. 0.18-/spl mu/m gate length) RF low-noise amplifiers (LNAs), based on Volterras series, is presented. Compact and accurate frequency-dependent closed-form expressions describing the effects of the different transistor parameters on harmonic distortion are derived. For the first time, the second-order distortion (HD2), in CMOS short-channel based LNAs, is studied. This is crucial for systems such as homodyne receivers. Equations describing third-order intermodulation distortion in RF LNAs are reported. The analytical analysis is verified through simulations and measured results of an 0.18-/spl mu/m CMOS 5.8-GHz folded-cascode LNA prototype chip geared toward sub-1-V operation. It is shown that the distortion is independent of the gate-source capacitance C/sub gs/ of the MOS transistors, allowing an extra degree of freedom in the design of LNA circuits. Distortion-aware design guidelines for RF CMOS LNAs are provided throughout the paper.

30-100-MHz NPN-only variable-gain class-AB instantaneous companding filters for 1.2-V applications

Two variations of a continuous-time instantaneous companding filter were integrated in a 25 GHz bipolar process. Their -3-dB frequencies are tunable in the ranges of 1-30 and 30-100 MHz. The DC gains are controllable up to 10 dB. The measured dynamic ranges for a 1% total harmonic distortion are 62.5 and 50 dB, for the 30 and 100 MHz filters, respectively. At maximum cutoff frequencies, the filters dissipate 6.5 mW from a 1.2 V supply.

RF CMOS fully-integrated heterodyne front-end receivers design technique for 5 GHz applications

This paper presents an architecture that allows the implementation of fully integrated heterodyne 5GHz RF receivers. The front-end circuitry consists of a low noise amplifier, a critical cascade of two notch filters, an active mixer, and a voltage controlled oscillator. The notch filters, which use on chip inductor Q-factor enhancement techniques, are designed to provide a wide bandwidth of image rejection (IR), eliminating the need for accurate IR tuning circuitry. More than 40dB of image rejection can be obtained in a standard 0.18/spl mu/m CMOS technology, for a 400MHz bandwidth centered at 7.2GHz, without having to resort to the overhead and the complexity of automatic tuning circuits. Design issues of homodyne and heterodyne 5GHz front-end receivers are received and discussed.

Distortion in RF CMOS short channel low noise amplifiers

An approach to estimate the distortion in CMOS short-channel (0.18 /spl mu/m gate length) RF low noise amplifiers (LNA), based on Volterras series, is presented. Compact and accurate frequency-dependent closed form expressions describing the effects of the different transistor parameters on harmonic distortion are derived. For the first time, the second order distortion (HD2), which is crucial in homodyne receivers, is studied. The analytical analysis is verified through simulations and measured results of a 0.18 /spl mu/m CMOS 5.8GHz folded-cascode LNA prototype chip geared towards sub-IV operation. Distortion-aware design guidelines for RF CMOS LNAs are provided throughout the paper.

A new CMOS charge pump for low-voltage (1V) high-speed PLL applications

This paper proposes a new charge pump structure for phase locked loop (PLL) applications. The circuit is optimized to minimize the amount of glitches in the output current. It is designed in a standard CMOS 0.18/spl mu/m technology, and it operates from a 1V power supply. The output voltage has a relatively wide range, from 100mV up to 900mV, and does not exhibit any spurious jump phenomenon. Simulation results in HSPICE show the capability of high-frequency operation (500MHz), with very low-power consumption (60/spl mu/W).

30-100 MHz npn-only variable-gain class AB companding-based filters for 1.2 V applications

Companding can be used to maintain reasonable dynamic range (DR) in integrated analog signal processors where the allowable voltage swings are limited by the low-voltage supply requirements of modern low-power applications. The input signal is compressed before being processed, which ensures signal integrity over a large range of signal levels. At the output, the signal is expanded to restore its dynamic range. This results in a higher output signal-to-noise ratio (SNR) compared to conventional analog signal processors. Unlike the latter, the higher SNR does not come at the expense of increased power dissipation or chip area for a given bandwidth. The dynamic range of low-voltage companding analog circuits can be significantly extended using class AB current mode based signal processors.

Robust multi-GHz (7.4GHz) on-chip image rejection in CMOS

The implementation of a robust, unconditionally stable, and high-Q image reject filter in standard CMOS is presented, enabling the realization of on-chip heterodyne receivers at 5 GHz and beyond. We propose the use of two cascaded notch filters, with slightly offsetted frequencies, resulting in a wide rejection bandwidth, thus eliminating the overhead of automatic tuning. A single-notch prototype achieves 62 dB of rejection at 7.4 GHz, and a double-notch design achieves 30 dB of rejection over 400 MHz

A low-power, 5-70 MHz, 7th-order filter with programmable boost, group delay, and gain using instantaneous companding

A seventh-order 0.05/spl deg/ equiripple linear-phase continuous-time filter employing, for the first time, instantaneous companding, was designed and integrated in a mature bipolar process. The amount of boost (up to 13 dB) and group-delay adjustment (30%) are digitally programmable. The DC gain is controllable up to 10 dB, and the -3 dB frequency (f/sub c/) is tunable from 5 to 70 MHz. The output swing for 1% TED is higher than 100m V/sub pp/, with a 1.5 V supply. The filter consumes very low power (5-13 mW for f/sub c/=70MHz) compared to conventional implementations (e.g. 120 mW for f/sub c/=100 MHz).

Distortion analysis of high-frequency log-domain filters using Volterra series

An approach to estimate the distortion in log-domain filters is presented. The models used for the bipolar transistors include the C/sub /spl pi// and C/sub sub/ parasitic capacitors, the beta effect, and the parasitic emitter resistances. Simple closed-form expressions describing the effect of each nonideality on distortion are derived and compared to simulations. A general method, which could be extended to analyze higher order filters, based on Volterra series, is used.