Mourad N. El-Gamal

A Highly Integrated 1.8 GHz Frequency Synthesizer Based on a MEMS Resonator

A highly integrated 1.7-2.0 GHz digitally programmable frequency synthesizer using a MEMS resonator as its reference is presented. Due to the dimensions of the MEMS device (e.g., 25 mum by 114 mum), the entire system with a total area of 6.25 mm2 can be housed in a small standard chip package. This considerably reduces the form factor and cost of the system, compared to using an external crystal as a reference. The MEMS resonators are clamped-clamped beams fabricated using a CMOS-compatible process. The main structural layer is made of silicon carbide, which provides the resonators with higher power handling capabilities and higher operating frequencies, compared to silicon. The resonators are electrostatically and thermally tunable - an 8.4% frequency tuning is demonstrated for a 9 MHz resonator. The 100 nm vertical transducer gaps of the resonators allow the use of electrostatic actuation voltages as low as 2 V. An integrated high gain-bandwidth trans-impedance amplifier (TIA) is combined with a resonator to generate the synthesizers input reference signal. The TIA employs automatic gain control to mitigate the inherent low power handling capabilities and the non-linearities of the MEMS device, thus minimizing their effect on phase noise. The fractional- N synthesizer employs a 3rd-order 20-bit delta-sigma modulator to deliver a theoretical output resolution of ~ 11 Hz, in order to allow for high output frequency stability when used with an appropriate feedback loop. A fully integrated on-chip dual path loop filter is used to maintain a high level of system integration. With a supply voltage of 2 V, the phase noise for a 1.8 GHz output frequency and a ~12 MHz reference signal is -122 dBc/Hz at a 600 kHz offset, and -137 dBc/Hz at a 3 MHz offset.

Ultra-wideband (UWB) communications systems: an overview

This paper presents an overview of the ultra-wideband (UWB) technology for wireless communications systems. Following a brief review of the UWB basic principles, the characteristics of application specific UWB wireless systems are described. Design principles and challenges of UWB wireless systems, with an emphasis on monolithic implementations are discussed. Trade-offs between performance, power consumption, and technology choices are addressed. Examples of state-of-the-art UWB circuits and systems are presented.

Distortion in RF CMOS short-channel low-noise amplifiers

An approach to estimate the distortion in CMOS short-channel (e.g. 0.18-/spl mu/m gate length) RF low-noise amplifiers (LNAs), based on Volterras series, is presented. Compact and accurate frequency-dependent closed-form expressions describing the effects of the different transistor parameters on harmonic distortion are derived. For the first time, the second-order distortion (HD2), in CMOS short-channel based LNAs, is studied. This is crucial for systems such as homodyne receivers. Equations describing third-order intermodulation distortion in RF LNAs are reported. The analytical analysis is verified through simulations and measured results of an 0.18-/spl mu/m CMOS 5.8-GHz folded-cascode LNA prototype chip geared toward sub-1-V operation. It is shown that the distortion is independent of the gate-source capacitance C/sub gs/ of the MOS transistors, allowing an extra degree of freedom in the design of LNA circuits. Distortion-aware design guidelines for RF CMOS LNAs are provided throughout the paper.

Gain and frequency controllable sub-1 V 5.8 GHz CMOS LNA

This paper presents the design and experimental results of a low-voltage low noise amplifier (LNA) with gain and frequency control in a standard 0.18 /spl mu/m CMOS process. Targeting at a center frequency of 5.8 GHz with a supply voltage of 1 V, the LNA exhibits a power gain of 13.2 dB with a noise figure of 2.5 dB. The circuit has over 10 dB of gain tuning, and 360 MHz of frequency tuning, and can operate at a supply voltage as low as 0.7 V.

Very high-frequency log-domain bandpass filters

A transistor-level all n-p-n differential log-domain integrator geared toward low-distortion very high-frequency (VHF) applications is proposed. Systematic design steps are suggested and used to realize second and higher order balanced bandpass filters, based on the method of operational simulation of doubly-terminated LC ladders. We discuss the special sensitivity of log-domain integrators to small dc biasing offsets, practical issues in the design of the input and output interface stages, and the effect of parasitic resistors and capacitors on high-frequency log-domain filters. Experimental results from a 0.8-/spl mu/m BiCMOS implementation of a single-ended 220-MHz biquad and a balanced 130-MHz fourth-order bandpass filter are reported, with emphasis on their distortion characteristics.

A Sub-mW, Ultra-Low-Voltage, Wideband Low-Noise Amplifier Design Technique

This paper presents a design methodology for an ultra-low-power (ULP) and ultra-low-voltage (ULV) ultra-wideband (UWB) resistive-shunt feedback low-noise amplifier (LNA). The ULV circuit design challenges are discussed and a new biasing metric for ULV and ULP designs in deep-submicrometer CMOS technologies is introduced. Series inductive peaking in the feedback loop is analyzed and employed to enhance the bandwidth and noise performance of the LNA. Exploiting the new biasing metric, the design methodology, and series inductive peaking in the feedback loop, a 0.5 V, 0.75-mW broadband LNA with a current reuse scheme is implemented in a 90-nm CMOS technology. Measurement results show 12.6-dB voltage gain, 0.1-7-GHz bandwidth, 5.5-dB NF, -9-dBm IIP3, and -18-dB P1dB while occupying 0.23 mm2.

Effects of transistor nonidealities on log-domain filters

Log-domain filtering makes explicit use of the diode nature of bipolar transistors to realize log-domain integrators, resulting in coupled translinear circuits. In this paper, the departure from ideal integration due to the major transistor nonidealities is studied, and practical filter deviation equations are derived. The device nonidealities to be tackled include: parasitic emitter resistance, finite beta, base resistance and Early effect. SPICE simulations, both large and small-signal analysis, are performed to verify the results. Compensation schemes are also proposed.

Recent advances and future trends in low power wireless systems for medical applications

This paper describes current state-of-the-art research on low power wireless systems for medical applications. Distinct design criteria and challenges in this area are addressed. A study of existing wireless technologies and their key applications are presented. A brief assessment of future trends for wireless medicine with a focus on emerging technologies is provided. Finally, a number of different energy-scavenging techniques for the future development of autonomous wireless nodes are reviewed.

LC ladder-based synthesis of log-domain bandpass filters

The design method of log-domain filters based on LC ladder synthesis is extended to cover a class of filter topologies which were not realizable otherwise. As an example, bandpass filters are considered. Known log-domain sub-circuits are combined together to realize a more versatile multiple-input log-domain integrator circuit. The realization of a second-order bandpass filter is discussed. A large signal analysis of the circuit shows how the gain, cutoff frequency, and Q-factor can be electronically and independently tuned. Experimental results are presented.

A Sub-1-V 4-GHz CMOS VCO and a 12.5-GHz oscillator for low-voltage and high-frequency applications

This paper presents the design and experimental measurements of four CMOS LC-based oscillators. The design methodologies of two different topologies and approaches for their optimization are presented. The first topology is optimized for low voltage operation in a 0.25-/spl mu/m process, which is demonstrated by a finest prototype, requiring only a 0.85-V power supply and reaching a maximum frequency of 4 GHz. A second circuit, using the same architecture in a 0.35-/spl mu/m process, oscillates at 5 GHz and operates from a 1.5-V power supply, while maintaining reasonable phase noise (-87.3 dBc/Hz @ 100 kHz offset). Finally, the third and fourth oscillators, based on a PMOS-NMOS complementary differential structure, were optimized for high frequency, reaching maximum oscillating frequencies of 10.5 GHz and 12.5 GHz, in a 0.35-/spl mu/m process. The oscillators make use of on-chip components only, allowing for simple and robust integration.