Roland Thewes

Sensor arrays for fully-electronic DNA detection on CMOS

A 16×8 DNA sensor array chip with fully electronic readout is based on an extended CMOS process. Requirements concerning the integration of bio-compatible interface-, sensor- and transducer-materials into a standard-CMOS-environment and circuitry design issues are discussed.

Vertical signal transmission in three-dimensional integrated circuits by capacitive coupling

In this paper, methods for direct vertical transmission of digital signals between adjacent chiplayers in three-dimensional circuit structures are presented. Alternative circuit schemes are investigated and compared to state-of-the-art structures with respect to signal delay and power dissipation. Improvements of over 30% in terms of speed and up to an order of magnitude in terms of dynamic power dissipation are achievable. Analytical calculations, simulations and experimental results show the suitability of the architectures for vertical signal transmission of high bandwidth digital information.

Biochemical sensors based on bulk acoustic wave resonators

A new general purpose approach for a sensor based on a mass-weighting principle has been developed. This concept offers the advantage to replace a complex and expensive optical system by a low-cost electronic readout system. In contrast to all established sensor principles the system only depends on the availability of specific probe molecules attached at the surface. The biochemical sensor principle is based on a film bulk acoustic wave resonator which detects mass differences on a biochemical prepared surface.

Intra-die device parameter variations and their impact on digital CMOS gates at low supply voltages

Statistical intra-die variations of device parameters from a 0.5 /spl mu/m CMOS process are determined, finding good agreement with the (WL)/sup -1/2/ model. It is proven that channel doping variations are responsible. Additionally, systematic proximity-induced parameter deviations due to different field oxide surroundings are found. The resulting variations of inverter delays for different supply voltages and gate areas are determined.

Explanation and quantitative model for the matching behaviour of poly-silicon resistors

We investigate the matching behaviour of poly-silicon resistors. Experimental results from an analog CMOS process with three poly-silicon options are discussed and compared with a quantitative model which is developed using fit parameter-free analytical calculations and Monte-Carlo simulations. It is found that mismatch is directly proportional to the grain size. A relation is derived that allows us to optimize devices for low mismatch circuit applications.

Hot-carrier degradation of p-MOSFET's under analog operation

The hot-carrier degradation of p-MOSFETs is investigated from the viewpoint of analog operation. We apply sensitive measurement methods to determine drain current, drain conductance, and transconductance in the saturation regime besides the commonly investigated parameters in the linear regime of operation. Those investigations are performed for different gate lengths in order to allow comparisons between the shortest channels used for digital and the long channels usually used for analog operation, it is found that the drain conductance important in many analog applications, does not show a channel length dependence for gate lengths above 1.5 times the minimum gate length. The stress time dependencies are determined predominantly finding logarithmic behaviors. These findings are explained by a model which highlights the importance of the lengths of the regions of damage and carrier velocity saturation. Moreover, the dependencies of the different characterization parameters on stress time, channel length and voltages of operation are evaluated. Finally, methods are given for extrapolation of degradation of analog parameters to operating conditions for reliability assurance.

Passive DNA Sensor with Gold Electrodes Fabricated in a CMOS Backend Process

A sensor for electrical detection of DNA is fabricated in a CMOS production line. A gold deposition process module is integrated in a CMOS backend process. The sensor principle is based on immobilization of singlestranded DNA probe molecules on an array consisting of interdigitated gold lines and subsequent hybridization with labeled target DNA strands. The electrical signal results from an electrochemical redox cycling process. Successful DNA detection experiments on the basis of such ‘passive’ chips are performed. This passive arrangement represents a test run for the extension of this principle to develop fully electronic DNA sensor arrays on active CMOS chips.

Effects of hot-carrier degradation in analog CMOS circuits

Abstract In this paper a method is presented that allows to quantify the effects of hot carrier degradation on analog CMOS circuits. Specific features of hot carrier degradation related to analog CMOS operation are discussed in detail. On this basis single transistor stress experiments are defined monitoring analog operation and conclusions are drawn for the choice of analog hot carrier lifetime criteria. A general method is presented which establishes a relation between single transistor stress results and circuit parameter degradation. Examples for the applicability of this method are given, presenting measured data of hot-carrier-induced parameter shifts of analog sub-circuits.

Technology aspects of a CMOS neuro-sensor: back end process and packaging

A CMOS-compatible process is presented which allows to realize sensor arrays for non-invasive, extracellular, high density, long term recording of neural activity. A high-permittivity biocompatible dielectric is used to capacitively couple nerve cell-induced biological signals to the CMOS circuitry-based electronic world. The transducer consists of a multi layer of TiO/sub 2/ and ZrO/sub 2/ and is fabricated in the backend of a 0.5 /spl mu/m standard CMOS technology. Living cells are cultured within a specific package on top of the sensor chip. First measurements reveal proper operation of the chip.

ROS: an extremely high density mask ROM technology based on vertical transistor cells

A novel mask-ROM technology enabling a twofold packing density compared to conventional, planar ROM layout relying on the same design rules is presented. The key of the new technology is a cell concept based on a vertical MOS transistor in a trench, and a doubling of the bitline pitch by use of the trench bottom as additional bitline. The features of the ROS-technology are demonstrated by means of a 1 Mbit demonstrator memory. Since vertical transistors are manufacturable far below channel lengths of 100 nm, the technology is very promising for mass storage and thus for the replacement of conventional mass storage devices by semiconductor-memories.