Franz Hofmann

Resistivity of porous silicon: a surface effect

Abstract For micro- and mesoporous silicon samples a decrease in conductivity by several orders of magnitude as compared with the substrate is observed. Since the structures in mesoporous silicon are too large to show significant quantum confinement, models for the decreased conduction based on quantum confinement are not applicable. A new model for the charge transport mechanism based on constrictions of conductive pathways produced by charged surface traps is proposed and verified in experiments.

Vertical MOS transistors with 70 nm channel length

Vertical nMOS transistors with channel lengths down to 70nm and thin gate oxides have been fabricated using LPCVD epitaxy for the definition of the channel region instead of fine line lithography. The devices show drain current and transconductance values comparable to very advanced planar transistors. For the shortest channel length a stronger increase of current is observed and is attributed to ballistic and floating substrate effects. Besides high saturation currents due to very short channel lengths a higher integration density seems to be feasible using this vertical transistor technology.

ROS: an extremely high density mask ROM technology based on vertical transistor cells

A novel mask-ROM technology enabling a twofold packing density compared to conventional, planar ROM layout relying on the same design rules is presented. The key of the new technology is a cell concept based on a vertical MOS transistor in a trench, and a doubling of the bitline pitch by use of the trench bottom as additional bitline. The features of the ROS-technology are demonstrated by means of a 1 Mbit demonstrator memory. Since vertical transistors are manufacturable far below channel lengths of 100 nm, the technology is very promising for mass storage and thus for the replacement of conventional mass storage devices by semiconductor-memories.

Planar gain cell for low voltage operation and gigabit memories

A dynamic gain memory cell has been fabricated which, despite its planar design, can compete with the area requirements of one transistor DRAM cells (1T-cells) built in trench or 3D stacked technology. The described gain cell can be geometrically shrunk because the drain current of scaled down MOS transistors increases resulting in higher signal charge. Another attractive feature of the proposed gain memory cell is that it can be fabricated using a CMOS logic process to bridge the gap between DRAM and CMOS logic technology. Because of its inherent amplification, the gain cell delivers even at supply voltages below 2 V sufficient signal charge making it suitable for low voltage applications.

Simulation of single electron circuits

A Monte Carlo simulator has been developed for the investigation of arbitrary single electron circuits. After a brief discussion of the fundamental effect we sketch the procedure used in the program. As an application, two circuits are analyzed under various conditions, especially considering possible high temperature operation.

Process- and Devicesimulation of Very High Speed Vertical MOS Transistors

Optical lithography does not allow the scaling of MOS transistors down to 100nm dimensions. Thus the channel length of high speed MOS devices must depend on alternative processing steps. In this work layer deposition and etching are analysed with respect to the formation of very short MOS transistors with vertical orientation. Dopant diffusion with very steep gradients are studied in epitaxial layers. Process and device engineering aspects for a vertical MOS transistor at the sidewall of an etched trench are discussed.