Rolf Drechsler

BDD-based synthesis of reversible logic for large functions

Reversible logic is the basis for several emerging technologies such as quantum computing, optical computing, or DNA computing and has further applications in domains like low-power design and nanotechnologies. However, current methods for the synthesis of reversible logic are limited, i.e. they are applicable to relatively small functions only. In this paper, we propose a synthesis approach, that can cope with Boolean functions containing more than a hundred of variables. We present a technique to derive reversible circuits for a function given by a binary decision diagram (BDD). The circuit is obtained using an algorithm with linear worst case behavior regarding run-time and space requirements. Furthermore, the size of the resulting circuit is bounded by the BDD size. This allows to transfer theoretical results known from BDDs to reversible circuits. Experiments show better results (with respect to the circuit cost) and a significantly better scalability in comparison to previous synthesis approaches.

RevLib: An Online Resource for Reversible Functions and Reversible Circuits

Synthesis of reversible logic has become an active research area in the last years. But many proposed algorithms are evaluated with a small set of benchmarks only. Furthermore, results are often documented only in terms of gate counts or quantum costs, rather than presenting the specific circuit. In this paper RevLib (www.revlib.org) is introduced, an online resource for reversible functions and reversible circuits. RevLib provides a large database of functions with respective circuit realizations. RevLib is designed to ease the evaluation of new methods and facilitate the comparison of results. In addition, tools are introduced to support researchers in evaluating their algorithms and documenting their results.

Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams

An efficient package for construction of and operation on ordered Kronecker Functional Decision Diagrams (OKFDD) is presented. OKFDDs are a generalization of OBDDs and OFDDs and as such provide a more compact representation of the functions than either of the two decision diagrams. In this paper basic properties of OKFDDs and their efficient representation and manipulation are presented. Based on the comparison of the three decision diagrams for several benchmark functions, a 25% improve ment in size over OBDDs is observed for OKFDDs.

Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques

Synthesis of reversible logic has become a very important research area in recent years. Applications can be found in the domain of low-power design, optical computing, and quantum computing. In the past, several approaches have been introduced that synthesize reversible networks with respect to a given function. Most of these methods only approximate a minimal network representation. In this paper, exact algorithms for the synthesis of multiple-control Toffoli networks are presented, i.e., algorithms that guarantee to find a network with the minimal number of gates. Our iterative algorithms formulate the synthesis problem as a sequence of decision problems. The decision problems are encoded as Boolean satisfiability (SAT) or SAT modulo theory (SMT) instances, respectively. As soon as one of these instances becomes satisfiable, a Toffoli network representation for the given function has been found. We show that choosing the encoding for synthesis is crucial for the resulting runtimes. Furthermore, we discuss the principal limits of the SAT and SMT approaches. To overcome these limits, we propose a method using problem-specific knowledge during synthesis. In addition, better embeddings to make irreversible functions reversible are considered. For the resulting synthesis problems, an improvement is presented that reduces the overall runtime by automatically setting the constant inputs to their optimal values. Experimental results on a large set of benchmarks demonstrate the differences between three exact synthesis algorithms. In addition, a comparison with the best-known heuristic results is provided. In summary, the results show that, for some benchmarks, the heuristic approaches have already found the minimal network, while for other benchmarks, significantly smaller networks exist.

RTL-Datapath Verification using Integer Linear Programming

Satisfiability of complex word-level formulas often arises as a problem informal verification of hardware designs described at the register transfer level (RTL). Even though most designs are described in a hardware description language (HDL), like Verilog or VHDL, usually this problem is solved in the Boolean domain, using Boolean solvers, These engines often show a poor performance for data path verification. Instead of solving the problem at the bit-level, a method is proposed to transform conjunctions of bitvector equalities and inequalities into sets of integer linear arithmetic constraints. It is shown that it is possible to correctly model the modulo semantics of HDL operators as linear constraints. Integer linear constraint solvers are used as a decision procedure for bitvector arithmetic. In the implementation we focus on verification of arithmetic properties of Verilog-HDL designs. Experimental results show considerable performance advantages over high-end Boolean SAT solver approaches. The speed-up on the benchmarks studied is several orders of magnitude.

Verifying UML/OCL models using Boolean satisfiability

Nowadays, modeling languages like UML are essential in the design of complex software systems and also start to enter the domain of hardware and hardware/software codesign. Due to shortening time-to-market demands, “first time right” requirements have thereby to be satisfied. In this paper, we propose an approach that makes use of Boolean satisfiability for verifying UML/OCL models. We describe how the respective components of a verification problem, namely system states of a UML model, OCL constraints, and the actual verification task, can be encoded and afterwards automatically solved using an off-the-shelf SAT solver. Experiments show that our approach can solve verification tasks significantly faster than previous methods while still supporting a large variety of UML/OCL constructs.

Binary decision diagrams in theory and practice

Abstract.Decision diagrams (DDs) are the state-of-the-art data structure in VLSI CAD and have been successfully applied in many other fields. DDs are widely used and are also integrated in commercial tools. This special section comprises six contributed articles on various aspects of the theory and application of DDs. As preparation for these contributions, the present article reviews the basic definitions of binary decision diagrams (BDDs). We provide a brief overview and study theoretical and practical aspects. Basic properties of BDDs are discussed and manipulation algorithms are described. Extensions of BDDs are investigated and by this we give a deeper insight into the basic data structure. Finally we outline several applications of BDDs and their extensions and suggest a number of articles and books for those who wish to pursue the topic in more depth.

On Acceleration of SAT-Based ATPG for Industrial Designs

Due to the rapidly growing size of integrated circuits, there is a need for new algorithms for automatic test pattern generation (ATPG). While classical algorithms reach their limit, there have been recent advances in algorithms to solve Boolean Satisfiability (SAT). Because Boolean SAT solvers are working on conjunctive normal forms (CNFs), the problem has to be transformed. During transformation, relevant information about the problem might get lost and, therefore, is not available in the solving process. In this paper, we present a technique that applies structural knowledge about the circuit during the transformation. As a result, the size of the problem instances decreases, as well as the run time of the ATPG process. The technique was implemented, and experimental results are presented. The approach was combined with the ATPG framework of NXP Semiconductors. It is shown that the overall performance of an industrial framework can significantly be improved. Further experiments show the benefits with regard to the efficiency and robustness of the combined approach.

Advanced Formal Verification

Preface. Contributing Authors. Introduction R. Drechsler. 1. Formal Verification. 2. Challenges. 3. Contributions to this Book. 1: What SAT-Solvers Can and Cannot Do E. Goldberg. 1. Introduction. 2. Hard Equivalence Checking CNF Formulas. 3. Stable Sets of Points. 2: Advancements in Mixed BDD and SAT Techniques G. Cabodi, S. Quer. 1. Introduction. 2. Background. 3. Comparing SAT and BDD Approaches: Are they Different? 4. Decision Diagrams as a Slave Engine in General SAT: Clause Compression by Means of ZBDDs. 5. Decision Diagram Preprocessing and Circuit-Based SAT. 6. Using SAT in Symbolic Reachability Analysis. 7. Conclusion, Remarks and Future Works. 3: Equivalence Checking of Arithmetic Circuits D. Stoffel, E. Karibaev, I. Kufareva, W. Kunz. 1. Introduction. 2. Verification Using Functional Properties. 3. Bit-Level Decision Diagrams. 4. Word-Level Decision Diagrams. 5. Arithmetic Bit-Level Verification. 6. Conclusion. 7. Future Perspectives. 4: Application of Property Checking R. Brinkmann, P. Johannsen, K. Winkelmann. 1. Circuit Verification Environment: Users View. 2. Circuit Verification Environment: Underlying Techniques. 3. Exploiting Symmetries. 4. Automated Data Path Scaling to Speed Up Property Checking. 5. Property Checking Use Cases. 6. Summary. 5: Assertion-Based Verification C.N. Coelho Jr, H.D. Foster. 1. Introduction. 2. Assertion Specification. 3. Assertion Libraries. 4. Assertion Simulation. 5. Assertions and Formal Verification. 6. Assertions and Synthesis. 7. PCI Property Specification Example. 8. Summary. 6: Formal Verification for Nonlinear Analog Systems W. Hartong, R. Klausen, L. Hedrich. 1. Introduction. 2. System Description. 3. Equivalence Checking. 4. Model Checking. 5. Summary. 6. Acknowledgement. Appendix: Mathematical Symbols. Index.

Implementing a multiple-valued decision diagram package

Decision diagrams are the state-of-the-art representation for logic functions, both binary and multiple-valued. Here we consider issues regarding the efficient implementation of a package for the creation and manipulation of multiple-valued decision diagrams (MDDs). In particular we identify issues that differ from binary decision diagram packages. We describe a matrix method for level interchange in MDDs that is essential for implementing variable reordering strategies. In addition, it is the basis for a novel approach to performing logic operations on MDDs, which we also present. Experimental results demonstrate the efficiency of this approach.