Nicole Drechsler

Multi-objective Optimisation Based on Relation Favour

Many optimisation problems in circuit design, in the following also refereed to as VLSI CAD, consist of mutually dependent sub-problems, where the resulting solutions must satisfy several requirements. Recently, a new model for Multi-Objective Optimisation (MOO) for applications in Evolutionary Algorithms (EAs) has been proposed. The search space is partitioned into so-called Satisfiability Classes (SCs), where each region represents the quality of the optimisation criteria. Applying the SCs to individuals in a population a fitness can be assigned during the EA run. The model also allows the handling of infeasible regions and restrictions in the search space. Additionally, different priorities for optimisation objectives can be modelled. In this paper, the model is studied in further detail. Various properties are shown and advantages and disadvantages are discussed. The relations to other techniques are presented and experimental results are given to demonstrate the efficiency of the model.

Fast exact minimization of BDD's

We present a new exact algorithm for finding the optimal variable ordering for reduced ordered binary decision diagrams (BDDs). The algorithm makes use of a lower bound technique known from very large scale integration design. Up to now this technique has been used only for theoretical considerations and it is adapted here for this purpose. Furthermore, the algorithm supports symmetry aspects and uses a hashing based data structure. Experimental results are given to demonstrate the efficiency of our approach. We succeeded in minimizing several functions, including adders with up to 64 variables, for which all other previously presented approaches fail.

Fast exact minimization of BDDs

We present a new exact algorithm for finding the optimal variable ordering for reduced ordered Binary Decision Diagrams (BDDs). The algorithm makes use of a lower bound technique known from VLSI design. Up to now this technique has been used only for theoretical considerations and if is adapted here for our purpose. Furthermore, the algorithm supports symmetry aspects and makes use of a hashing based data structure. Experimental results are given to demonstrate the efficiency of our approach. We succeeded in minimizing adder functions with up to 64 variables, while all other previously presented approaches fail.

Evolutionary Algorithms for Embedded System Design

Preface. Contributing Authors. Foreword D.E. Goldberg. Introduction R. Drechsler, N. Drechsler. 1. Evolutionary Testing of Embedded Systems J. Wegener. 2. Genetic Algorithm Based DSP Code Optimization R. Leupers. 3. Hierarchical Synthesis of Embedded Systems C. Haubelt, et al. 4. Functional Test Generation F. Ferrandi, et al. 5. Built-in Self Test of Sequential Circuits F. Corno, et al. Index.

Multi-objected Optimization in Evolutionary Algorithms Using Satisfiability Classes

Many optimization problems consist of several mutually dependent subproblems, where the resulting solutions must satisfy all requirements. We propose a new model for Multi-Objective Optimization (MOO) in Evolutionary Algorithms (EAs). The search space is partitioned into so-called Satisfiability Classes fSCj, where each region represents the quality of the optimization criteria. Applying the SCs to individuals in a population a fitness can be assigned during the EA run. The model also allows the handling of infeasible regions and restrictions in the search space. Additionally, different priorities for optimization objectives can be modeled. Advantages of the model over previous approaches are discussed and an application is given that shows the superiority of the method for modeling MOO problems.

Combining GAs and symbolic methods for high quality tests of sequential circuits

A symbolic fault simulator is integrated in a Genetic Algorithm (GA) environment to perform Automatic Test Pattern Generation (ATPG) for synchronous sequential circuits. In a two phase algorithm, test length and fault coverage as well are optimized. However, there are circuits with bad random testability properties, that are also hard to test using genetically optimized test patterns. Thus, deterministic aspects are included in the GA environment to improve fault coverage. Experiments demonstrate that tests with higher fault coverages and considerably shorter test sequences than in previously presented approaches are obtained.

Verification of designs containing black boxes

Often modern designs contain regions where the implementation of certain components is not (fully) known. These regions are called black boxes in the following. They occur e.g. if different designers work on a project in parallel or if IP cores are used. An approach based on a symbolic representation of characteristic functions for verifying circuits with black boxes is presented. We show that by this method more faults can be detected than with pure binary simulation and symbolic simulation using BDDs, respectively, only. This results from the formulation of our algorithm that allows implications over the black box. Experimental results are given to show what parts of a design can be proven to be correct, if black boxes are assumed. Of course, the probability for the detection of a fault in general depends on the size of the unknown regions. But fault injection experiments on benchmarks show that for many circuits, even up to 90% of the faults are detected, even though large parts of the design are unspecified.

Disjoint Sum of Product Minimization by Evolutionary Algorithms

Recently, an approach has been presented to minimize Disjoint Sum-of-Products (DSOPs) based on Binary Decision Diagrams (BDDs). Due to the symbolic representation of cubes for large problem instances, the method is orders of magnitude faster than previous enumerative techniques. But the quality of the approach largely depends on the variable ordering of the underlying BDD.

Minimizing the number of one-paths in BDDs by an evolutionary algorithm

Ordered binary decision diagrams (BDDs) are used in VLSI CAD, especially for the canonical representation of Boolean functions. In the last decade, the method of choice for optimizing this data structure was minimizing the number of nodes in the associated graph. However, recent works have shown that the number of paths is also important. In this work, minimizing the number of one-paths of BDDs is accomplished by an evolutionary algorithm (EA) acting on the permutation of variables. The optimal operator weights for the EA were determined by a parameter study. Experimental results demonstrate the efficiency of our approach.

Heuristic Learning Based on Genetic Programming

In this paper we present an approach to learning heuristics based on Genetic Programming (GP) which can be applied to problems in the VLSI CAD area. GP is used to develop a heuristic that is applied to the problem instance instead of directly solving the problem by application of GP. The GP-based heuristic learning method is applied to one concrete field from the area of VLSI CAD, i.e. minimization of Binary Decision Diagrams (BDDs). Experimental results are given in order to demonstrate that the GP-based method leads to high quality results that outperform previous methods while the run-times of the resulting heuristics do not increase. Furthermore, we show that by clever adjustment of parameters, further improvements such as the saving of about 50% of the run-time for the learning phase can be achieved.