Roma Dasgupta

SALT, a dedicated readout chip for high precision tracking silicon strip detectors at the LHCb Upgrade

The Upstream Tracker (UT) silicon strip detector, one of the central parts of the tracker system of the modernised LHCb experiment, will use a new 128-channel readout ASIC called SALT. It will extract and digitise analogue signals from the UT sensors, perform digital signal processing and transmit a serial output data. The SALT is being designed in CMOS 130 nm process and uses a novel architecture comprising of analog front-end and fast (40 MSps) ultra-low power (<0.5 mW) 6-bit ADC in each channel. The prototype ASICs of important functional blocks, like analogue front-end, 6-bit SAR ADC, PLL, and DLL, were designed, fabricated and tested. A prototype of an 8-channel version of the SALT chip, comprising all important functionalities was also designed and fabricated. The architecture and design of the SALT, together with the selected preliminary tests results, are presented.

Performance of the INTPIX6 SOI pixel detector

Characterization of the monolithic pixel detector INPTIX6, designed at KEK and fabricated in Lapis 0.2 μ m Fully-Depleted, Low-Leakage Silicon-On-Insulator (SOI) CMOS technology, was performed. The INTPIX6 comprises a large area of 1408 × 896 integrating type squared pixels of 12 micron pitch. In this work the performance and measurement results of the prototypes produced on lower resistivity Czochralski type (CZ-n) and high resistivity floating zone (FZ-n) sensor wafers are presented. Using 241Am radioactive source the noise of INTPIX6 was measured, showing the ENC (Equivalent Noise Charge) of about 70 e−. The resolution calculated from the FWHM of the Iron-55 X-ray peak was about 100 e−. The radiation hardness of the SOI pixel detector was also investigated. The CZ-n type INTPIX6 received a dose of 60 krad and its performance has been continuously monitored during the irradiation.

IOP : 8-channel prototype of SALT readout ASIC for Upstream Tracker in the upgraded LHCb experiment

SALT is a new 128-channel readout ASIC for silicon strip detectors in the upgraded Upstream Tracker of the LHCb experiment. It will extract and digitise analogue signals from the sensor, perform digital processing and transmit serial output data. SALT is designed in CMOS 130 nm process and uses a novel architecture comprising of an analogue front-end and an ultra-low power (<0.5 mW) fast (40 MSps) sampling 6-bit ADC in each channel. An 8-channel prototype (SALT8), comprising all important functionalities was designed, fabricated and tested. A full 128-channel version was also submitted. The design and test results of the SALT8 prototype are presented showing its full functionality.

Ultra-Low Power Fast Multi-Channel 10-Bit ADC ASIC for Readout of Particle Physics Detectors

The design and measurement results of an ultra-low power multi-channel fast 10-bit Analog-to-Digital Converter (ADC) ASIC, developed for readout systems in future particle physics experiments, are discussed. An 8-channel prototype with a PLL-based data serialization and a fast data transmission was designed and fabricated in a 130 nm CMOS process. The ADC converts analog data with sampling rates from about 10 kS/s to 40 MS/s, with power consumption proportional to sampling rate. The resulting Figure of Merit (FOM), for sampling rates 5-40 MS/s, is 35-42 fJ/conv.-step, per ADC channel. Similar power contribution is spent for fast data serialization and the largest contribution goes to data transmission. A wide spectrum of static and dynamic measurements confirm very good performance of this multi-channel ADC with ENOB ~9.2 bits, an excellent channel uniformity, and negligible crosstalk. The ADC works asynchronously and so it is not limited to systems with uniform time sampling. The ADC is designed using dynamic circuitry which eliminates static power consumption (except leakage), as a consequence it is ready for applications requiring power cycling.

Development of pixel detector in Novel sub-micron technology SOI CMOS 200 nm

This paper presents the design of a new monolithic Silicon-On-Insulator pixel sensor in 200 nm SOI CMOS technology. The main application of the proposed pixel detector is the spectroscopy, but it can also be used for the minimum ionising particle (MIP) tracking in particle physics experiments. For this reason the overriding goal of the project was to increase the signal to noise ratio of the readout circuit and sensor.

Signal coupling to embedded pitch adapters in silicon sensors

Abstract We have examined the effects of embedded pitch adapters on signal formation in n-substrate silicon microstrip sensors with data from beam tests and simulation. According to simulation, the presence of the pitch adapter metal layer changes the electric field inside the sensor, resulting in slowed signal formation on the nearby strips and a pick-up effect on the pitch adapter. This can result in an inefficiency to detect particles passing through the pitch adapter region. All these effects have been observed in the beam test data.

Silicon pixel detector prototyping in SOI CMOS technology

The Silicon-On-Insulator (SOI) CMOS is one of the most advanced and promising technology for monolithic pixel detectors design. The insulator layer that is implemented inside the silicon crystal allows to integrate sensors matrix and readout electronic on a single wafer. Moreover, the separation of electronic and substrate increases also the SOI circuits performance. The parasitic capacitances to substrate are significantly reduced, so the electronic systems are faster and consume much less power. The authors of this presentation are the members of international SOIPIX collaboration, that is developing SOI pixel detectors in 200 nm Lapis Fully-Depleted, Low-Leakage SOI CMOS. This work shows a set of advantages of SOI technology and presents possibilities for pixel detector design SOI CMOS. In particular, the preliminary results of a Cracow chip are presented.

Design and simulations of the 10-bit SAR ADC in novel sub-micron technology 200 nm SOI CMOS

This paper presents the design of the 10-bit Successive Approximation Register Analog-to-Digital Converter (SAR ADC) achieving 20 MHz sampling frequency at a power consumption of about 900 μW and 1.8 V power supply. The ADC was designed in 200 nm Silicon-On-Insulator (SOI) CMOS process. The SOI is one of the most advanced CMOS technology that allows to reduce the parasitic capacitances, limit power dissipation and increase speed of the system.