Szymon Bugiel

Development of low-power high speed (10Gb/s) drivers in CMOS 130 nm technology

The aim of this work is to develop a dedicated low power transmitter interface for high-speed data transmission in CMOS 130 nm technology. Such interface is necessary in complex ASICs working at high frequencies and processing large amounts of data, in particular it is needed in advanced detector readout systems of particle physics experiments. New multichannel readout ASICs, capable to transmit data at high frequencies (>5Gb/s), with low jitter, and consuming very low power, are recently being intensively developed. A Current Mode Logic (CML) and Source-Series Terminated (SST) interfaces are natural candidates to drive the data out of the chip. A broadband extension techniques using inductors may be applied to extend the bandwidth of these drivers. Unfortunataly, inductors occupy very large area what limits their applications in ASICs. In this work the CML driver using inductive peaking and two SST drivers (with, without series peaking) were developed to achieve transmission speeds between 5-10 Gb/s, together with very low (<;2 ps) jittter. We present and compare the schematic and post-layout simulations of the developed drivers together with all relevant parameters (speed, jitter, eye diagram). Prototype designs in CMOS 130 nm were already submitted and are now in fabrication.

Ultra-Low Power Fast Multi-Channel 10-Bit ADC ASIC for Readout of Particle Physics Detectors

The design and measurement results of an ultra-low power multi-channel fast 10-bit Analog-to-Digital Converter (ADC) ASIC, developed for readout systems in future particle physics experiments, are discussed. An 8-channel prototype with a PLL-based data serialization and a fast data transmission was designed and fabricated in a 130 nm CMOS process. The ADC converts analog data with sampling rates from about 10 kS/s to 40 MS/s, with power consumption proportional to sampling rate. The resulting Figure of Merit (FOM), for sampling rates 5-40 MS/s, is 35-42 fJ/conv.-step, per ADC channel. Similar power contribution is spent for fast data serialization and the largest contribution goes to data transmission. A wide spectrum of static and dynamic measurements confirm very good performance of this multi-channel ADC with ENOB ~9.2 bits, an excellent channel uniformity, and negligible crosstalk. The ADC works asynchronously and so it is not limited to systems with uniform time sampling. The ADC is designed using dynamic circuitry which eliminates static power consumption (except leakage), as a consequence it is ready for applications requiring power cycling.

Development of radiation-hard bandgap reference and temperature sensor in CMOS 130 nm technology

A stable reference voltage (or current) source is a standard component of todays microelectronics systems. In particle physics experiments such reference is needed in spite of harsh ionizing radiation conditions, i.e. doses exceeding 100 Mrads and fluences above 1e15 n/cm2. After such radiation load a bandgap reference using standard p-n junction of bipolar transistor does not work properly. Instead of using standard p-n junctions, two enclosed layout transistor (ELTMOS) structures are used to create radiation-hard diodes: the ELT bulk diode and the diode obtained using the ELTMOS as dynamic threshold transistor (DTMOS). In this paper we have described several sub-1V references based on ELTMOS bulk diode and DTMOS based diode, using CMOS 130 nm process. Voltage references the structures with additional PTAT (Proportional To Absolute Temperature) output for temperature measurements were also designed. We present and compare post-layout simulations of the developed bandgap references and temperature sensors, which show correct operation (<;1mV bandgap stability, linear PTAT) in teperature range -20 to 100 celsius degree.

Development of pixel detector in Novel sub-micron technology SOI CMOS 200 nm

This paper presents the design of a new monolithic Silicon-On-Insulator pixel sensor in 200 nm SOI CMOS technology. The main application of the proposed pixel detector is the spectroscopy, but it can also be used for the minimum ionising particle (MIP) tracking in particle physics experiments. For this reason the overriding goal of the project was to increase the signal to noise ratio of the readout circuit and sensor.

Signal coupling to embedded pitch adapters in silicon sensors

Abstract We have examined the effects of embedded pitch adapters on signal formation in n-substrate silicon microstrip sensors with data from beam tests and simulation. According to simulation, the presence of the pitch adapter metal layer changes the electric field inside the sensor, resulting in slowed signal formation on the nearby strips and a pick-up effect on the pitch adapter. This can result in an inefficiency to detect particles passing through the pitch adapter region. All these effects have been observed in the beam test data.

Silicon pixel detector prototyping in SOI CMOS technology

The Silicon-On-Insulator (SOI) CMOS is one of the most advanced and promising technology for monolithic pixel detectors design. The insulator layer that is implemented inside the silicon crystal allows to integrate sensors matrix and readout electronic on a single wafer. Moreover, the separation of electronic and substrate increases also the SOI circuits performance. The parasitic capacitances to substrate are significantly reduced, so the electronic systems are faster and consume much less power. The authors of this presentation are the members of international SOIPIX collaboration, that is developing SOI pixel detectors in 200 nm Lapis Fully-Depleted, Low-Leakage SOI CMOS. This work shows a set of advantages of SOI technology and presents possibilities for pixel detector design SOI CMOS. In particular, the preliminary results of a Cracow chip are presented.

Design and simulations of the 10-bit SAR ADC in novel sub-micron technology 200 nm SOI CMOS

This paper presents the design of the 10-bit Successive Approximation Register Analog-to-Digital Converter (SAR ADC) achieving 20 MHz sampling frequency at a power consumption of about 900 μW and 1.8 V power supply. The ADC was designed in 200 nm Silicon-On-Insulator (SOI) CMOS process. The SOI is one of the most advanced CMOS technology that allows to reduce the parasitic capacitances, limit power dissipation and increase speed of the system.