Ron-Yi Liu

A CT sigma-delta modulator with a hybrid loop filter and capacitive feedforward

A CT (continuous-time) sigma-delta modulator (CT ΣΔM) clocked at 128 MHz with a hybrid active-passive loop filter is presented for WCDMA applications. This 5th-order loop filter architecture mainly consists of two passive integrators and three active integrators. To erase the summation amplifier used in the CIFF (chain of integrators with weighted feedforward summation) topology, the capacitive feedforward structure is employed. In addition, local feedback resistors are formed as the bridge-T network to reduce the chip area. After chip being fabricated in TSMC 0.18 µm 1.8 V CMOS technology, the overall measured results have achieved dynamic range of 62 dB over a 2 MHz signal bandwidth, SNDR of 60.26 dB, IM3 of −48 dB and power dissipation of 9 mW. Including pads, the overall chip area is 0.642 (1.07 × 0.6) mm2.

The 10 GHz wide tuning and low phase-noise PLL chip design

An integer-N phase-locked loop (PLL) operating at 10 GHz is designed and fabricated in TSMC 0.18-um CMOS technology. The proposed PLL with a LC-tank voltage-controlled oscillator (VCO) and a mixed design of current mode logic (CML) and true single phase clock (TSPC) logic in the frequency divider achieves a tuning range from 8.75 GHz to 10.93 GHz and a phase noise of −113.4 dBc per Hertz at an offset frequency of 1 MHz from the carry frequency of 10.49 GHz. The final simulated locking time is lower than 3.7 us. Including pads and an on-chip third-order low-pass filter, the overall chip area is only 0.82×0.68 mm2 (0.56 mm2) as well as the power consumption is 39 mW at the 1.8 V supply voltage.

Chip design of an 8 MHz CMOS switched-capacitor low-pass filter for signal receiver applications

In this paper, a fifth-order elliptical low-pass filter using switched-capacitor (SC) architecture is proposed. The filter has a pass-band of 8 MHz and clock frequency of 80 MHz. The proposed filter is realized by cascades of first-order and second-order biquad building blocks. In order to reach the largest possible input dynamic range and save chip area, the method of dynamic range scaling and minimum capacitor scaling is used. Measurement results show that the proposed SC low-pass filter achieves a pass-band frequency of 8.72 MHz. The chip area including pads is 0.895 mm2 and the power dissipation is 44.2 mW at the supply voltage 1.8 V.

The RF receiver front-end chip design with the transformer balun for DSRC applications

A 0.18 µm CMOS RF receiver front-end applying in DSRC systems is presented in this paper. The proposed receiver front-end includes the current-reused LNA, the folded Giber cell mixer, and the Colpitts VCO. Also, this paper presents the design methodology and application of the transformer balun for RFIC. The measured results of the proposed receiver front-end show the input return loss of 30.5 dB, the conversion gain of 17.5 dB, the (DSB) NF of 4.2 dB, and the third-order intercept point (IIP3) of −10 dBm at 5.8 GHz frequency. The chip area of the proposed receiver front-end including pads is 1.4 × 1.4 mm with the total power dissipation of 49.78 mW.

A high performance continuous-time sigma-delta modulator with a 2 MHz bandwidth hybrid loop filter for wireless healthcare applications

A continuous-time (CT) sigma-delta (ΣΔ) modulator clocked at 128 MHz with a hybrid active-passive loop filter is presented for wireless and wearable technologies in healthcare systems. The proposed 5th-order loop filter architecture mainly consists of two passive integrators, three active integrators, 2-bit flash analog-to-digital converter (ADC), and a current steering digital-to-analog converter (DAC). To erase the summation amplifier used in the chain of integrators with weighted feedforward summation (CIFF) topology, the capacitive feedforward structure is employed. In addition, local feedback resistors are designed to form the bridge-T network to reduce the chip area. The prototype chip is fabricated with TSMC 0.18 μm CMOS technology. Under the supply voltage of 1.8 V, measured results have achieved a dynamic range of 67 dB over a 2 MHz signal bandwidth, a SNDR of 63.3 dB, an ENOB of 10.2 bits, IM3 of 60 dB and a power dissipation of 9.52 mW including 8.1 mW of analog power. Including pads, the chip area is 0.8365 (1.195 × 0.7) mm2.

Chip Design of an UWB, High Gain and Low Noise Amplifier for Wireless Applications

An ultra-wideband (UWB), high gain and low-noise amplifier (LNA) for wireless applications is presented in this paper. Operating at the frequency band of 0.8-6.0 GHz and fabricated in TSMC 0.18-um technology, the measured results show the gain of 17-19 dB, the noise figure (NF) less than 4.8 dB, the input third-order intercept point (IIP3) of -17 dBm, the reverse isolation less than -25 dB and the power dissipation of 43.2 mW at 1.8 V voltage supply. The chip area including pads is only 1.027mm2.

Chip Design of a Low-Voltage Wideband Continuous-Time Sigma-Delta Modulator with DWA Technology for WiMAX Applications

This paper presents the design and experimental results of a continuous-time (CT) sigma-delta (ΣΔ) modulator with data-weighted average (DWA) technology for WiMAX applications. The proposed modulator comprises a third-order active RC loop filter, internal quantizer operating at 160 MHz and three DAC circuits. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero (NRZ) DACs are adopted to reduce clock jitter sensitivity. The NRZ DAC circuits with quantizer excess loop delay compensation are set to be half the sampling period of the quantizer for increasing modulator stability. A dynamic element matching (DEM) technique is applied to multi-bit ΣΔ modulators to improve the nonlinearity of the internal DAC. This approach translates the harmonic distortion components of a nonideal DAC in the feedback loop of a ΣΔ modulator to high-frequency components. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. The DWA technique is used for reducing DAC noise due to component mismatches. The prototype is implemented in TSMC 0.18 um CMOS process. Experimental results show that the ΣΔ modulator achieves 54-dB dynamic range, 51-dB SNR, and 48-dB SNDR over a 10-MHz signal bandwidth with an oversampling ratio (OSR) of 8, while dissipating 19.8 mW from a 1.2-V supply. Including pads, the chip area is 1.156 mm2.

Chip design of phase-locked loop for ISM band applications

A TSMC 0.35um CMOS 2P4M process PLL (phase-locked loop) for ISM band applications is proposed. The PLL, with a crossed-coupled pMOS ring-oscillator VCO, is realized without using any inductor. Measurement results show that at the supply voltage of 3.3 V and the lowest reference frequency of 25 MHz, the locking range is from 1.8 GHz to 3.29 GHz, locking time is less than 3 us and the phase noise is −107.1 dBc/Hz at 1 MHz offset. The total power consumption of the PLL is 85.4 mW at center frequency of 2.48 GHz. The core chip area is only 0.17 mm2 and including pad, it is 1.02 mm2.