Wen-Cheng Lai

Chip design of a 5.6-GHz 1-V wide tuning range frequency synthesizer with Gm-boosting Colpitts VCO for biomedical application

A 5.6-GHz 1-V wide tuning range frequency synthesizer with a gain-boosting Colpitts voltage-controlled oscillator (VCO) is fabricated in TSMC 0.18 um CMOS process. In this prototype, there are two important features. First, a 1-V gain-boosting Colpitts LC VCO circuit is adopted to reduce phase noise and power consumption. Second, a class-AB current mode logic (CML) circuit is utilized in first divider stage to deal with the high frequency signal. At the supply voltages of 1-V for VCO and 1.8-V for digital circuits, measured results achieve that the VCO output frequency is tunable from 5.13~5.98 GHz corresponding to 15.4% and the locked phase noise is -105.83 dBc/Hz at 1MHz from 5.15 GHz. The power consumption is 5.6 mW and including pads, the chip area is 0.632 (0.89 × 0.71) mm2. This chip design low power consumption for biomedical application.

Low Power VCO and Mixer for Computing Miracast and Mobile Bluetooth Applications

A new fully integrated, low power voltage controlled oscillator and divider for Bluetooth and Miracast application are presented. The power consumption use charge recycling technique to reduced current from the divider. This circuit was implemented in 0.18 um CMOS technique with 1.8 V supply voltage. The broadband CMOS double-balance mixer for RF receiver is presented. The broadband mixer is fabricated with the 0.18 μm CMOS process. Measurement of the CMOS mixer is performed; input return loss is higher than 8.5 dB. For VCO with divider measured results indicate the frequency is tunable from 1.91 GHz to 2.07 GHz, corresponding to 13 %. The phase noise of the VCO operating at 2 GHz is -116.8 dBc/Hz at 1 MHz offset, while the VCO draws 2.61 mA and 4.7 mW consumption at frequency band from a 1.8 V supply. Including pads. The output power is -15.85 dBm with 50- O termination at the frequency o f of 2 GHz and the calculated FOM (figure of merit) is -176.

Design of frequency synthesizer with VCO charged by near infrared for bioinformatics and healthcare wireless applications on robotic nurses

This paper presents a wide tuning, low phase noise, and fast locking CMOS frequency synthesizer with 1.8V power supply. The proposed design is operating frequency range of the proposed design is ranged for the local oscillator of the RF front-end circuits. The phase-locked loop (PLL) frequency synthesizer is implemented in TSMC 0.18 μm CMOS process. The main features include the uses of a gate-to-source feedback Colpitts voltage-controlled oscillator (VCO) to lower phase noise, and an off-chip tunable low-pass filter to compensate the variations of resistance R and capacitance C to speed locking time and reduce chip area. This chipset has built in near-infrared laser-driven (NIRLD) might be a promising wireless electrical power source technology with human body. This chip can sense ECG and EMG signal and wireless transfer to robotic nurses. The computational biology and bioinformatics sent to healthcare center or research hospital from robotic nurses in control intelligence.

Integrated chip design of a 10GHz band voltage controlled oscillator and charge-injected mixer with low phase noise and wide tuning range.

A simple low phase noise and wide tuning range voltage-controlled oscillator (VCO) is designed for 10 GHz band application. The proposed oscillator adopts a complementary cross-coupled pair LC-VCO circuit with only one symmetrical inductor and implemented in TSMC 0.18-um CMOS process. A 10 GHz broadband CMOS double-balance mixer for communication receiver is presented. The broadband mixer is fabricated with low power 0.18 μm standard CMOS process. Measurement of the integrated mixer is performed as chipset input return loss is higher than 8.5 dB. At the supply voltage of 1.8 V, measured results achieve a tuning range of 9.6 to 11.08 GHz, corresponding to 13.9 %, a phase noise under -115.1 dBc/Hz at a 1 MHz offset frequency from 10.02 GHz with a tuned control voltage from 0 to 1.7 V and an output power of -2.231 dBm at 50-Ω termination and at 10.02 GHz. The power consumption is 3.58 mW and the chip area including pads is 0.61×0.66 (0.37) mm2. The proposed VCO, without the need of any off-chip device, is well suitable for mobile cellular networks applications.

Chip design of a high performance LC-VCO and mixer charge-injection signal processing for WiMAX communication and internet application

A high performance current-reused CMOS LC-voltage-controlled oscillator (LC-VCO) for WiMAX communication and internet application is fabricated in TSMC 0.18-μm CMOS process. The proposed VCO applies the complementary cross-coupled technique and uses differentially tuned accumulation MOS varactors. Measured results achieve 27.86% frequency tuned range when biased between 0-1.8 V, tunable output frequency from 2.81 to 3.71 GHz, output power of -5.54 dBm and phase noise of -122 dBc/Hz at 1 MHz offset from lower frequency of 2.816 GHz, and good value of FOM (Figure of Merit) of -180.8 dBc/Hz. The broadband CMOS double-balance mixer for wireless is presented. The broadband mixer is fabricated with the 0.18 μm CMOS process. Measurement of the CMOS mixer is performed, the input return loss is higher than 8.5 dB. The chip area including pads is only 0.488 mm2 and the power dissipation including buffers is 13.5 mW.

A low power quadrature and divide-by-two frequency VCO design mixer with charge-injection for biomedical applications

A new fully integrated, low power complementary cross-coupled quadrature voltage-controlled oscillator (QVCO), divide-by-two frequency divider and double-balance mixer for biomedical applications are presented. The features of our proposed circuit are using charge recycling technique to reduce current from the divider, employing adaptive body-biasing technique (ABB) to drop the minimum voltage clearance of the VCO and achieving two quadrature frequencies which are 2.0 GHz and 4.0 GHz bands. The VCO use differentially tuned MOS varactors can diminish the bad effect of high varactor sensitivity by excluding the common-mode noise. The proposed QVCO and double-balance mixer were implemented in 0.18 um CMOS process with 1.8 V supply voltage, is employed to modulate a wireless communication signal for proposed interactive intelligent healthcare monitoring system (IIHMS). Measured results indicate the divider output frequency is tunable from 1.91 GHz to 2.07 GHz and the QVCO output is from 3.82 GHz to 4.14 GHz, corresponding to 8.05 %. The phase noise of the QVCO operating at 2.02 GHz is -121.8 dBc/Hz at 1 MHz offset. This QVCO draws 2.61 mA and 4.7 mW power consumption. The output power is -17.15 dBm with a 50-Ω load at the frequency of 2.02 GHz. The broadband CMOS double-balance mixer input return loss is higher than 8.5 dB.

Wide-band divide-by-4 injection-locked frequency divider using RLC resonator and capacitive cross-coupled oscillator

A wide locking range divide-by-4 injection-locked frequency divider (ILFD) using a standard 0.18 μm CMOS process is presented. The ILFD circuit is realized with a capacitive cross-coupled n-core MOS dual-resonance RLC-tank oscillator to extend the locking range. The core power consumption of the ILFD core is 11.872 mW. The dividers free-running frequency has dual-bands at 2.87 and 2.69 GHz by switching the varactors control bias, and at the incident power of 0 dBm the locking range is 3.2 GHz (28.82%), from the incident frequency 9.5 to 12.7GHz.

An 8-bit 2 MS/s successive approximation register analog-to-digital converter for bioinformatics and computational biology Application

In this paper, a 1.8-V 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) implemented in TSMC 0.18-um CMOS process is presented. By applying SAR control logic that reduces half comparator and digital circuit power consumption, the proposed SAR ADC achieves low power consumption. Also, bootstrapped switch method is used to solve varying on-resistance of analog sampling switch caused from varying input signal. Measured results show that at the supply voltage of 1.8 V and sampling rate of 2 MS/s, the proposed SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 42.7 dB, an effective number of bits (ENOB) of 6.8 bits, a differential nonlinearity (DNL) of 0.98 LSB, an integral nonlinearity (INL) of 2.01 LSB and a power consumption of 128 μW. The overall chip area is only 0.67 mm2 with a small ADC core area of 0.226 mm2 for bioinformatics and computational Application.

Low power injection-locked frequency divider using native MOS

This paper presents a 0.55V and low power divided-by-2 injection-locked frequency divider (ILFD) using native nMOS as the injection MOSFET with threshold voltage nearly equal to 0. At the injection power of 0dBm, the measured locking range is from 6.1 to 7.45 GHz. Excluding output buffers the ILFD consumes the power 0.69 mW under a standard supply of 0.55 V.

A continuous-time low-pass sigma-delta ADC chip design for LTE communication application and bio-signal acquisitions

This paper presents a continuous time lowpass sigma-delta ADC for LTE communication with a chain of integrators and with capacitive feedforward summation (CICFF) plus circuit - which is an ideal function for implementation in low power applications. The summation of feedforward signals is achieved by capacitors plus, without the essential thing of any extra active components which can be used for electroencephalogram (EEG) or electrocardiogram (ECG) signal acquisition systems. The quantizer uses a 1-bit comparator which can achieve high linearity easily. The chip was implemented in 1.8 V supply voltage which works as a part of the biological signal acquisition system. Tested results have achieved a dynamic range of 52 dB over a 5 MHz signal bandwidth, a peak SNDR of 55.33 dB and power dissipation of 24.5 mW.