Ronald Kakoschke

Modelling of wafer heating during rapid thermal processing

A theory of wafer heating during rapid thermal processing is presented. It is demonstrated that temperature uniformity is not only limited by radiation loss at the wafer edge in the stationary state but also influenced by transient effects during temperature ramping. Whereas a compensation of edge losses call for enhanced illumination intensities at the wafer periphery, the avoidance of transient temperature gradients would require uniform illumination. Calculations for various system configurations lead to optimized processing cycles and suggest possible improvements of RTP equipment.

The appearance of spatially nonuniform temperature distributions during rapid thermal processing

Rapid thermal processing (RTP) of silicon wafers is a promising technique for submicron device structures. Heating is achieved by an intense light-source which allows one to obtain very high temperatures in very short times. Problems arise from temperature gradients. Both experiments and theoretical calculations show that a nonuniform lamp intensity improves the temperature uniformity only in a stationary state when only nonuniform back-reflection of heat radiation by the reflector has to be compensated. This measure, however, causes a dramatic transitory nonuniformity which hampers future applications of RTP especially with larger wafer sizes. The deteriorating influence is demonstrated with shallow junction formation, plastic deformation of the wafer (slip), and aluminum alloying as examples.

Progress in speed power performance of bipolar technology by sub-10 keV B implantation into amorphized Si

Double polysilicon self-aligned bipolar n-p-n transistors have been fabricated with very narrow base widths by using very low-energy ion implantation of B at 2, 5, and (for comparison) 10 keV. To prevent channeling of B ions during implantation, several samples are amorphized by Ge ion implantation prior to the /sup 11/B implant. A two-step annealing cycle with minimum thermal budget is described which meets the requirements for defect-free recrystallization of the amorphous layer and the damaged region while simultaneously avoiding, as far as possible, diffusion broadening of the B profile. These optimal conditions result in transistors with cutoff frequencies up to 28 GHz (at V/sub CB/=3 V) and CML ring oscillators with 3.7-mW power consumption per gates at a minimum delay time of 35 ps/gate.<<ETX>>