Andreas Kux

Latent defect detection in microcontroller embedded flash test using device stress and wordline outlier screening

For automotive microcontroller products constant effort is spent to drive failure rate well into the sub-dpm region [1]. While in the logic parts of automotive microcontrollers scan-testing is able to account for high degrees of test coverage, embedded flash has to take additional measures to achieve such target e.g. using various flash pattern to cover array and periphery for topological failure modes at critical bias conditions. With such failure modes being widely suppressed, latent defects come into focus. In this paper a latent defect detection method is presented allowing to screen for macroscopic defects on flash word lines that do not cause an easily detectable fatal failure but a performance marginality that only after customer use results in field failure. The basis of this test is on one hand a package test concept allowing for considerable device stress, on the other hand an access-time shmoo into regions tighter than customer spec to identify extrinsic behavior of affected word lines. With these measures introduced to safe launch backend (BE) test the corresponding failure mode has been reduced to an extent that no failure analysis request (FAR) case has been observed for two years volume.

Charge trapping in ONO interpoly dielectric of FLOTOX EEPROM cells

The threshold voltage loss of erased FLOTOX EEPROM cells with various ONO interpoly dielectric layers has been studied as a function of bake time and programming pulse amplitude. The results show a displacement of electrons injected into the nitride layer to be the root cause of the threshold voltage lowering. A quantitative model has been used for optimizing the cell layer construction as well as the cell operating conditions with respect to a minimized programming voltage at a maximum data retention.