Ronald N. Legge

Rapid thermal annealing of Si implanted GaAs

Rapid thermal annealing (RTA) technology offers potential advantages for GaAs MESFET device technology such as reducing dopant diffusion and minimizing the redistribution of background impurities. LEC semi-insulating GaAs substrates were implanted with Si at energies from 100 to 400 keV to doses from 1 × 1012 to 1 × 1014/cm2. The wafers were encapsulated with Si3N4 and then annealed at temperatures from 850-1000° C in a commercial RTA system. Wafers were also annealed using a conventional furnace cycle at 850° C to provide a comparison with the RTA wafers. These implanted layers were evaluated using capacitance-voltage and Hall effect measurements. In addition, FET’s were fabricated using selective implants that were annealed with either RTA or furnace cycles. The effects of anneal temperature and anneal time were determined. For a dose of 4 × 1012/cm2 at 150 keV with anneal times of 5 seconds at 850, 900, 950 and 1000° C the activation steadily increased in the peak of the implant with overlapping profiles in the tail of the profiles, showing that no significant diffusion occurs. In addition, the same activation could be obtained by adjusting the anneal times. A plot of the equivalent anneal times versus 1/T gives an activation energy of 2.3 eV. At a higher dose of 3 × 1013 an activation energy of 1.7 eV was obtained. For a dose of 4 × 1012 at 150 keV both the RTA and furnace annealing give similar activations with mobilities between 4700 and 5000 cm2/V-s. Mobilities decrease to 4000 at a dose of 1 × 1013 and to 2500 cm2/V-s at 1 × 1014/cm2. At doses above 1 × 1013 the RTA cycles gave better activation than furnace annealed wafers. The MESFET parameters for both RTA and furnace annealed wafers were nearly identical. The average gain and noise figure at 8 GHz were 7.5 and 2.0, respectively, for packaged die from either RTA or furnace annealed materials.

A Comparison of RTO and Furnace Oxides

The original intent of this study was to compare rapid thermal, thin (80-100A) gate oxides with standard, furnace-grown, thin gate oxides for endurance. Wafer processing before gate oxide growth was chosen to duplicate processing used ina typical non-volatile memory product. In particular, care was taken to duplipate pre- and post- gate growth processing of field oxide isolated polysilicon capacitors for all wafers in order to eliminate the previous difficulties in comparing oxides when different cleans and processing steps are used.[1] Substrate defects, atypical to this process, were presumably introduced during the initial wafer cleaning and scattered the time-to-breakdown (TTB) values during a constant current stress of these oxides to the point where statistical comparison of TTB averages was dubious. However, for unannealed wafers and for post polysilicon definition heat treatments of 900 ° C, RTO oxides grown with HCL had the same oxide trapping rate as the furnace oxides grown with TCA and RTO oxides grown in pure O 2 had a faster trapping rate. Higher temperature post polysilicon definition heat treatments had different effects. RTO oxides exhibited better yield than the furnace oxides. These results illustrate the differences between RTO and furnace oxidation in the presence of non-ideal wafer substrates.

Polycrystalline silicon solar cells from recrystallized plasma deposited thin films

Large grain polycrystalline silicon films are produced by a two step process involving plasma deposition of microcrystalline silicon films on a substrate, separation from the substrate, and subsequent grain enhancement of the silicon films. The effects of doping and substrate temperature during deposition on the solar cell conversion efficiency are investigated. Effects of ppm level molybdenum contamination from the substrate, and silicon microstructure after grain enhancement, on solar cell efficiency parameters are also investigated. Solar cells with efficiencies of up to 10.1% under AM1 illumination, were fabricated on these silicon films.

Redistribution of Ion Implanted Hydrogen in Polycrystalline Silicon Thin Films

The effect of implanted hydrogen on the resistivity of polycrystalline silicon films has been investigated. The observed reduction in resistivity due to hydrogen is most pronounced for lightly doped films, and is accentuated by a 450°C anneal. An increase in Hall mobility is also observed. The pre-implant resistivity is completely recovered by annealling at 600°C. Diffusion of hydrogen at low temperatures is monitored by local resistivity changes detected with spreading resistance measurements.