Roopak Sinha

Efficient WCRT analysis of synchronous programs using reachability

Static computation of the worst-case reaction time (WCRT) is required for the real-time execution of synchronous programs. Existing approaches use model checking or integer linear programming. we formulate this as an abstraction-based reachability analysis yielding a lower worst case complexity. Benchmarking shows a significant overall speed-up of 64-times over existing approaches.

A Model Checking Approach to Protocol Conversion

System-on-chip verification is an active research area. Of particular interest is protocol conversion, where two components with different protocols are controlled to communicate accurately. We present an approach to protocol conversion using model checking. The temporal logic ACTL is used to describe desired behaviour and finite state machines are used for protocol description. We use tableau-based converter construction and prove that a converter exists only when a successful tableau can be constructed. Liveness is incorporated so that converters satisfy additional constraints on protocol communication. A NuSMV-based implementation has been created and we present results on various problems including a large NuSMV example.

Observer based verification of IEC 61499 function blocks

IEC 61499 is an international standard for designing Industrial Process Control Systems using artefacts such as Function Blocks and Execution Control Charts. The existing approaches towards formal verification of function blocks lack the natural expression for specifying the system properties. We suggest an approach for performing formal verification of IEC 61499 designs using observers expressed as function blocks. This method provides the IEC 61499 designer with an intuitive way of expressing system properties and also makes the verification result easier to map to the original design. We have implemented two different algorithms, a tableau based CTL model checker and a reachability analyzer, to support the verification of observers. Experimental evaluation over a range of benchmarks have shown better performance as compared to Esterel based verification in terms of computation time.

Automatic test case generation from requirements for industrial cyber-physical systems

Abstract Industrial cyber-physical systems require complex software to orchestrate heterogeneous mechatronic components and control physical processes. This software is typically developed and refined iteratively in a model-driven fashion. Testing such multi-dimensional systems is extremely difficult as subsequent refinements may not correspond accurately with previous system models. We propose a framework to generate test-cases from functional requirements at all stages in the model-driven engineering process. A requirements ontology initially created during requirements engineering is iteratively refined such that test-cases can be generated automatically. An industrial water process system case study illustrates the strengths of the proposed formalism. We also present an automatic test-case generation and execution tool called REBATE (REquirements Based Automatic Testing Engine).

Hardware Acceleration of SVM-Based Classifier for Melanoma Images

Melanoma is the most aggressive form of skin cancer which is responsible for the majority of skin cancer related deaths. Recently, image-based Computer Aided Diagnosis CAD systems are being increasingly used to help skin cancer specialists in detecting melanoma lesions early, and consequently reduce mortality rates. In this paper, we implement the most compute-intensive classification stage in the CAD onto FPGA, aiming to achieve acceleration of the system for deploying as an embedded device. A hardware/software co-design approach was proposed for implementing the Support Vector Machine SVM classifier for classifying melanoma images online in real-time. The hybrid Zynq platform was used for implementing the proposed architecture of the SVM classifier designed using the High Level Synthesis design methodology. The implemented SVM classification system on Zynq demonstrated high performance with low resources utilization and power consumption, meeting several embedded systems constraints.

Multi-clock SoC design using protocol conversion

The automated design of SoCs from pre-selected IPs that may require different clocks is challenging because of the following issues. Firstly, protocol mismatches between IPs need to be resolved automatically before IPs are integrated. Secondly, the presence of multiple clocks makes the protocol conversion even more difficult. Thirdly, it is desirable that the resulting integration is correct-by-construction, i.e., the resulting SoC satisfies given system-level specifications. All of these issues have been studied extensively, although not in a unifying manner. In this paper we propose a framework based on protocol conversion that addresses all these issues. We have extensively studied many SoC design problems and show that the proposed methodology is capable of handling them better than other known approaches. A significant contribution of the proposed approach is that it nicely generalizes many existing techniques for formal SoC design and integrates them into a single approach.

Hierarchical and Concurrent ECCs for IEC 61499 Function Blocks

IEC 61499 enables component-oriented descriptions of complex industrial processes facilitating model-driven engineering. One aspect that is lacking, however, is the ability to directly express Statecharts-like hierarchy and concurrency within basic function blocks (BFBs). Such features can significantly enhance function blocks and help create more succinct and readable specifications. We propose a new syntactic extension to the standard called hierarchical and concurrent execution control chart (HCECC). A major roadblock for any suggested changes to the standard is the need for compliance. Our approach extends the synchronous execution semantics of IEC 61499, where HCECCs are purely syntactic sugar. Using a revised synchronous semantics, our compiler generates standard compliant C code from HCECCs. Benchmarking and usability studies reveal the relative superiority of the proposed approach over existing approaches.

Virtual Traffic Lights+: A Robust, Practical, and Functionally Safe Intelligent Transportation System

The latest advancements in intelligent transportation systems (ITSs) increasingly rely on wireless vehicle-to-vehicle (VTV) and vehicle-to-infrastructure (VTI) communications to manage traffic flows at intersections dynamically. A prominent example is virtual traffic lights (VTLs), which use only VTV communications and which have been shown to have the potential to increase traffic flows and reduce emissions significantly. Two key issues that can affect the adoption of desirable ITS solutions like VTLs are functional safety and the management of a move from a vehicle fleet not equipped with VTLs to a vehicle fleet completely equipped with VTLs. For the first issue, the first model-driven engineering-based modeling and verification technique for ITSs is proposed. This technique can be used to prove functional safety with 100% coverage. Through the use of this technique, it is shown that although VTLs are safe under normal circumstances, they are very fragile when they face unlikely, but not impossible, exceptional circumstances. For the second issue, an extended algorithm called VTL+ is proposed. VTL+ uses additional VTI communication with the existing infrastructure to enable effective and safe traffic flow during the VTL transition phase. It is also found through static analysis that VTL+ is more robust and more feature rich than VTLs.

Local Module Checking for CTL Specifications

Model checking is a well known technique for the verification of finite state models using temporal logic specification. While model checking is suitable for transformational systems (also called closed systems), it is unsuitable for open systems (also known as reactive systems) where the nondeterminism in the environment must be considered during verification. Module checking is an approach for the verification of open systems which have both closed (internal) and open (environment or external) states. It has been demonstrated in [Orna Kupferman, Moshe Y. Vardi, and Pierre Wolper. Module checking. Information and Computation, 164:322-344, 2001] that the complexity of module checking branching time logic CTL is EXPTIME-complete. The approach to module checking is global and the method tries to establish that the property in question holds over all possible environments. This papers develops a local approach to CTL module checking using tableau rules. The proposed approach tries to determine a single environment under which the negation of the property is satisfied over the given module. Such a strategy, thus, leads to a local approach to module checking where we only explore states that are relevant to proving that the negation of the property can be satisfied over the given module using an appropriate witness (environment) that the algorithm also generates. While the worst case complexity of our algorithm is identical to the earlier complexity, we demonstrate that practical implementation of the proposed approach is feasible and yields much better results than the global approach.

Correct-by-Construction Approaches for SoC Design

This book describes an approach for designing Systems-on-Chip such that the system meets precise mathematical requirements. The methodologies presented enable embedded systems designers to reuse intellectual property (IP) blocks from existing designs in an efficient, reliable manner, automatically generating correct SoCs from multiple, possibly mismatching, components.