Parthasarathi Roop

SystemJ compilation using the tandem virtual machine approach

SystemJ is a language based on the Globally Asynchronous Locally Synchronous (GALS) paradigm. A SystemJ program is a collection of GALS nodes, also called clock domains, and each clock domain is a synchronous program that extends the Java language. Initial compilation of SystemJ has been to standard Java executing on a Java Virtual Machine (JVM), which is both inefficient and bulky for small embedded systems. This article proposes a new approach for compiling and executing SystemJ using a new type of virtual machine, called a Tandem Virtual Machine (TVM). The TVM approach provides an efficient implementation of SystemJ on both standard processors and resource-constrained embedded processors. The new approach is based on separating the control-driven and data-driven operations for execution on two virtual machines. While the JVM executes the data-driven operations, a Control Virtual Machine (CVM) is introduced to execute the control-driven parts of a SystemJ program. The TVM approach is capable of handling all data-driven and control-driven operations required by the GALS model. The benchmark results show that the TVM has code size improvements of over 60% on average and also a substantial improvement in execution speed over standard Java-based compilation.

Correct-by-Construction Approaches for SoC Design

This book describes an approach for designing Systems-on-Chip such that the system meets precise mathematical requirements. The methodologies presented enable embedded systems designers to reuse intellectual property (IP) blocks from existing designs in an efficient, reliable manner, automatically generating correct SoCs from multiple, possibly mismatching, components.

Design of Distributed Heterogeneous Embedded Systems in DDFCharts

The use of formal models of computation in dealing with increasing complexity of embedded systems design is gaining attention. A successful model of computation must be able to handle both control-dominated and data-dominated behaviors, which are most often simultaneously present in complex embedded systems. Besides behavioral heterogeneity, direct support for modeling distributed systems is also desirable, since an increasing number of embedded systems belong to this category. In this paper, we present distributed DFCharts (DDFCharts), a language based on a formal model that targets distributed heterogeneous embedded systems. Its top hierarchical level is made suitable to capture distributed systems. Behavioral heterogeneity is addressed by composing finite-state machines (FSMs) and synchronous dataflow graphs (SDFGs). We illustrate modeling in DDFCharts with practical examples and describe its implementation on heterogeneous target architecture.

Hybrid automata models of cardiac ventricular electrophysiology for real-time computational applications

Virtual heart models have been proposed for closed loop validation of safety-critical embedded medical devices, such as pacemakers. These models must react in real-time to off-the-shelf medical devices. Real-time performance can be obtained by implementing models in computer hardware, and methods of compiling classes of Hybrid Automata (HA) onto FPGA have been developed. Models of ventricular cardiac cell electrophysiology have been described using HA which capture the complex nonlinear behavior of biological systems. However, many models that have been used for closed-loop validation of pacemakers are highly abstract and do not capture important characteristics of the dynamic rate response. We developed a new HA model of cardiac cells which captures dynamic behavior and we implemented the model in hardware. This potentially enables modeling the heart with over 1 million dynamic cells, making the approach ideal for closed loop testing of medical devices.Virtual heart models have been proposed for closed loop validation of safety-critical embedded medical devices, such as pacemakers. These models must react in real-time to off-the-shelf medical devices. Real-time performance can be obtained by implementing models in computer hardware, and methods of compiling classes of Hybrid Automata (HA) onto FPGA have been developed. Models of ventricular cardiac cell electrophysiology have been described using HA which capture the complex nonlinear behavior of biological systems. However, many models that have been used for closed-loop validation of pacemakers are highly abstract and do not capture important characteristics of the dynamic rate response. We developed a new HA model of cardiac cells which captures dynamic behavior and we implemented the model in hardware. This potentially enables modeling the heart with over 1 million dynamic cells, making the approach ideal for closed loop testing of medical devices.

The AMBA SOC Platform

ARM is one of the most widely used processor in modern SoCs such as mobile phones. This chapter presents the internals of typical SoCs from an ARM perspective. This includes the internals of the AMBA family of buses and associated IPs. We provide an in-depth description of the buses and associated timing. We then elaborate on how to formally represent a bus transaction using the well known concept of finite state machines (FSMs).

Models for SoCs and Specifications

In order to perform system-level verification of SoCs, it is essential to not only model the on-chip IP protocols but also high-level requirements that describe the desired sequencing of control flow and data-flow between these IPs. This chapter provides the concept of SoC boiler plates. These provide an approach by which engineers can capture correctness criteria of a SoC at the system-level using “structured English” requirements. We then show how these can be automatically mapped to temporal logic formula. This chapter also introduces a type of finite state machine called synchronous Kripke structures (SKS). These are used for the formal representation of on-chip communication protocols of the IPs. This chapter may be viewed as the “requirements / specification” chapter.

Related Work and Outlook

Chapter 7 summarizes related work. We discuss the system-level verification literature and SoC design literature. Key concepts covered in this chapter include literature related to requirements, modelling and analysis techniques for component-based design of systems.

Automatic Protocol Conversion

Chapter 6 provides further details of the converter synthesis algorithm. Key concepts covered in this chapter include data-buffers and data-related properties, converter definition and control, and the converter generation algorithm. We provide a classification of the inputs and outputs of a converter. Then the converter is formalized and its control actions are described using an example. The details of this algorithm with an appropriate illustration appears in Appendix A. This chapter may be viewed as the “converter synthesis” chapter.

SoC Design Methodology

Chapter 5 provides an SoC design approach, where on-chip protocols are described as SKS and requirements are captured as boiler plates. It then develops an approach called oversampling to bridge the clock mismatches between IPs. Finally, it uses an approach based on “converter synthesis” to propose the design methodology. The concepts in this chapter are illustrated using a set-top box example. This chapter may be viewed as the “correct-by-construction design methodology” chapter.

Automatic Verification Using Model and Module Checking

As a precursor to system-level verification of SoCs, we present two well known verification techniques for closed and open systems respectively. Closed systems are “transformational” in nature and evolve without any need for external intervention. We present model checking, as an approach for the verification of closed systems. Open systems, in contrast, are “reactive” in nature and evolve based on interactions with an external environment. Typical applications of SoCs in the embedded system domain are open in nature. We present module checking as an automated technique for the verification of open systems. Both model checking and module checking are “formal” algorithms and hence require mathematical models to describe the system model (Kripke structures) and the desired properties (CTL).