Rosario D'Esposito

A Geometry Scalable Model for Nonlinear Thermal Impedance of Trench Isolated HBTs

This letter presents a geometry scalable approach for the calculation of temperature dependent thermal impedance (ZTH) in trench-isolated heterojunction bipolar transistors. The model is capable of predicting the ZTH at any desired temperature and bias points. The temperature dependency is derived by discretizing the heat flow region into n number of elementary slices depending on the thermal gradient. Temperature dependent thermal resistances Rths and capacitances Cths for each of the slices are calculated in a self-consistent manner. Finally, the proposed model is validated with low-frequency measurements at different ambient temperatures (Tamb) for different transistor geometries and found to be in good agreement.

Analytic Estimation of Thermal Resistance in HBTs

In this paper, we propose a new method for estimating the peak junction temperature and thermal resistance in modern heterojunction bipolar transistors (HBTs). The proposed method uses the temperature dependence of thermal conductivity of the material. The method is analytic in nature and does not require any iteration as opposed to the existing state-of-the-art model. This analytic method can easily include the available scaling relations relevant to specific technology to estimate the junction temperatures and thermal resistances of the corresponding transistors. The analytic model is tested against iterative self-consistent solutions for simple structures without any trench isolation and for structures corresponding to the ST Microelectronics B9MW technology that includes shallow and deep trench isolations. The model is slightly modified in order to include the effects from the back-end-of-line metal layers. The resulting analytic model is validated against the measured results for silicon germanium HBTs fabricated in ST Microelectronics B9MW technology.

A study on transient intra-device thermal coupling in multifinger SiGe HBTs

This paper presents a study of transient mutual thermal coupling occurring between the fingers of trench isolated SiGe HBTs. Three-dimensional thermal TCAD simulations have been carried out to obtain the temperature evolution in transient operation in a multifinger HBT structure. The same behavior has been simulated using a netlist-based model, which provides an accurate representation of the substrate thermal coupling between active device areas. On-wafer measurements in pulsed conditions have been conducted on specially designed test structures that permit to determine the thermal coupling between the different fingers of a 5x(CBEBC) SiGe HBT; the results from the measurements are found to be in good agreement with a simulation in which the thermal coupling network has been added to the thermal nodes of five HiCuM transistor models.

An improved scalable self-consistent iterative model for thermal resistance in SiGe HBTs

In this paper we present an improved self-consistent iterative model for thermal resistance in SiGe HBTs. The proposed model evaluates both the upward and downward heat dissipation from the heat source located at the base-collector junction. Along with the temperature dependency, thermal conductivity degradation due to heavy doping and Ge composition in the base region is included in the proposed model. It is observed that the model accuracy is improved once these physical effects are included along with the upward heat diffusion. Scalability of the proposed model is validated with the measured data for different emitter geometries.

Compact Model Validation Strategies Based on Dedicated and Benchmark Circuit Blocks for the mm-Wave Frequency Range

This paper presents a methodology for compact model evaluation and validation at circuit level for RF and mm-wave applications. Accurate compact models are a prerequisite for efficient circuit design but currently modeling engineers lack of suitable verification procedures. In this work we detail a methodology to fulfill these requirements together with circuit examples, starting from the simplest differential pair to the most advanced four stage differential LNA working at 220GHz. It is shown that a complete hierarchy of validation circuits (from the simplest circuit to the most complex) provides a new perspective with respect to the crucial task of model qualification but also directions for future compact model developments.

Substrate-coupling effect in BiCMOS technology for millimeter wave applications

This paper presents a detailed analysis of substrate coupling effects. Two types of coupling are considered. (i) Coupling from the device to the substrate and (ii) coupling between two neighboring devices. To assess the substrate coupling effect, specific test-structures have been designed for the mmW characterization. Various devices dimensions and distance between two neighboring devices have been fabricated for investigation. In addition, the associated deembedding structures have also been added on the test-structure such as the open, short, open and open-pad structures. Finally, S parameters measurements are performed up to 110 GHz and the substrate-coupling is investigated. To validate the analysis, Sentaurus TCAD simulations are used. A comparison between the S-parameters measurements and TCAD results is given. Finally, a scalable compact model based on lumped elements is proposed for the circuit design in the sub-THz range.

Efficient modeling of static self-heating and thermal-coupling in multi-finger SiGe HBTs

A computationally efficient model for static self-heating and thermal coupling in a multi-finger bipolar transistor is proposed. Compared to an existing state-of-the-art model, our model differs only in the implementation strategy keeping the physical basis intact. The formulated model is implemented in Verilog-A without using any voltage controlled voltage sources. Temperature dependence of the thermal resistances are considered within the framework of the model. The number of extra nodes in our model reduces to 2n from n2 required in the state-of-the-art model with n as the number of emitter fingers in a transistor. The simulation results of our model are found to be identical with those of the state-of-the-art model demonstrating the capability of accurately considering the static self-heating and thermal coupling in a simple way. The model is found to accurately predict the measured data of a five-finger transistor. It is found that in high current operating regimes, our five finger transistor model simulates around 11% faster compared with the state-of-the-art model.

Extraction of BEOL Contributions for Thermal Resistance in SiGe HBTs

In this brief, we propose a simple approach to extract the contribution of the back-end-of-line (BEOL) layers on the thermal resistance of heterojunction bipolar transistors (HBTs). A finite value of BEOL thermal resistance obtained following our approach confirms a non-negligible heat flow toward BEOL. The proposed extraction technique is validated with iterative solutions and measured data of silicon–germanium HBTs fabricated in the STMicroelectronics B9MW technology.

Innovative SiGe HBT Topologies With Improved Electrothermal Behavior

This paper investigates alternative topologies of silicon germanium heterojunction bipolar transistors designed and fabricated in the state-of-the-art BiCMOS process from STMicroelectronics for improved safe-operating characteristics. Electrical and thermal behaviors of various structures are analyzed and compared, along with a detailed discussion on drawbacks and advantages. The test structures under study are different in terms of emitter-finger layouts as well as the metal stacks in the back-end-of-line. It is observed that the multifinger transistor structures having nonuniform finger lengths with wider area enclosed by the deep trench and higher metallization stacks yield an improved thermal behavior. Therefore, the safe-operating area of multifinger transistors can be extended without degrading the RF performances.

Accurate Modeling of Thermal Resistance for On-Wafer SiGe HBTs Using Average Thermal Conductivity

An accurate analytic model is proposed for estimating the junction temperature and thermal resistance in silicon–germanium heterojunction bipolar transistors (SiGe HBTs) including the back-end-of-line (BEOL) metal layers. The model uses an average value of thermal conductivity in order to include the temperature dependence of thermal resistance. The parameters corresponding to the thermal conductivity and the BEOL thermal resistance used in the model are extracted following a recently reported methodology. The proposed model is scalable in nature and verification with experimental data shows an excellent accuracy across different emitter geometries of SiGe HBTs fabricated in STMicroelectronics B9MW technology. Compact model simulations show that the proposed model simulates around 23% faster compared with an existing state-of-the-art iterative method.