Roseanne Duca

4-dimensional design analysis and optimization of system-in-package

This paper is an overview of applications of CAE (computer-aided-engineering) in design for package and board level reliability of system-in-package (SiP). CAE is an efficient tool for virtual prototyping of complex SiP to save the development time and cost with understanding on the physics of failures. The paper highlights on five major reliability issues frequently encountered in the development of SiP, such as thermomechanical related package failures, matrix package warpage, moisture-induced package failures, board level solder joint reliability under thermal cycling test and drop test. For each individual topic, introduction, brief theory, and an example of application with correlation to experiment are given

Investigation of warpage in wafer-level Molding: Measurements and FE analysis

Novel 3D packaging technologies which require large area mold embedding are being developed in order to achieve further minimization and cost reductions. Compression molding using epoxy molding compounds is one technique being considered for wafer-level encapsulation. However significant warpage in molded wafers is a critical issue which may hinder successive processes from being carried out. Cases of both symmetric (spherical) and asymmetric (cylindrical)-shaped warpage have been reported in wafer-level compression molding trials on blank wafers. This paper presents finite element models of the molded wafer, with and without embedded dies, which take into account the observed complex multi-state warpage characteristics. Molded wafer warpage measurements were carried out in order verify the applicability of the small and large deformation theories for layered plates, to deduce the cure shrinkage molding compound properties and to validate the finite element model of the molded blank wafer. The latter was used to analyze possible factors (nonplanar mold layer thickness, anisotropic wafer elastic properties) leading to asymmetric warpage. The numerical model will thus enable the prediction of the optimum process and material conditions for the warpage to be minimized together with the expected deformation of the molded wafer model with embedded dies.

Warpage issues in large area mould embedding technologies

The need for higher communications speed, heterogeneous integration and further miniaturisation have increased demand in developing new 3D integrated packaging technologies which include wafer-level moulding and chip-to-wafer interconnections. Wafer-level moulding refers to the embedding of multiple chips or heterogeneous systems on the wafer scale. This can be achieved through a relatively new technology consisting of thermal compression moulding of granular or liquid epoxy moulding compounds. Experimental measurements from compression moulding on 8” blank wafers have shown an unexpected tendency to warp into a cylindrical-shape following cooling from the moulding temperature to room temperature. Wafer warpage occurs primarily as a result of a mismatch between the coefficient of thermal expansion of the resin compound and the Si wafer. This paper will delve into possible causes of such asymmetric warpage related to mould, dimensional and material characteristics using finite element (FE) software (ANSYS Mechanical). The FE model of the resin on wafer deposition will be validated against the measurement results and will be used to deduce appropriate guidelines for low warpage wafer encapsulation.