Kim-yong Goh

Challenges for extra large embedded wafer level ball grid array development

Fan-out embedded wafer level ball grid array (eWLB) is a very promising packaging technology with many advantages in comparison to standard Ball Grid Array Packages and leadframe based packages because of smaller size, better electrical and thermal performance, higher package interconnect density and system integration possibilities at low packaging cost. It was successfully developed for medium and large-size package. However, there is strong need to develop extra large eWLB for system integration. Compared with large eWLB, there are many challenges for extra large eWLB development. Wafer or panel level warpage, package level reliability, and board level reliability are ones of the most challenging issues. In this paper, finite element modeling was used to create design rules and optimize test vehicles based on the correlation done for medium, large-size eWLB. Two test vehicles were indentified for process development and reliability test. Recent progress in the extra large eWLB development is introduced in this paper, the results show that the design rule and process capability are reliable and ready for extra large molded embedded wafer level package for system integration needs.

Finite Element Analysis of Thermal Cycling Reliability of an Extra Large Thermally Enhanced Flip Chip BGA Package with Rotated Die

Since the introduction of Thermally Enhanced Flip Chip Ball Grid Array (TEFCBGA) packages, it has been one of the popular packaging options in the market for mid to high end devices in that it effectively improves both electrical and thermal performance of the product. However, to develop a robust TEFCBGA package with extra large body size of 55 mm × 55 mm is a no easy task, especially when it contains a Cu/Low-k die of 19 mm × 19 mm in size at the same time. The presence of such a large sized die not only brings about reliability issues, e.g. delamination at Inter-Layer Dielectric (ILD) interfaces, die cracking, early flip chip bump fatigue failure and excessive package warpage, but takes up most of the precious substrate real estate available, leaving little room for the neighboring passive components. To cope with this space constraint, the die is proposed to rotate by 45° with regard to the package outline, whereby a much more flexible layout of passive devices can be achieved. However, it has yet to answer whether this modified die arrangement creates more problems than it solves. This paper initially investigated the BGA and flip chip solder joint reliability of the baseline TEFCBGA package, i.e. with standard die layout, under board level Accelerated Thermal Cycling (ATC) test through Finite Element Analysis (FEA). Global-local and multi-level sub-modeling techniques were employed for modeling of BGA solder balls and FC solder bumps respectively. Experiments were then carried out to assess the accuracy of the FEA model.

Thermal cycling fatigue model development for FBGA assembly with Sn-Ag-based lead-free solder

With the increasing requirement for lead-free solders, it is desired to know how different solder alloys affect on reliability of microelectronic assembly. Some fatigue life models for Sn-Ag-Cu (SAC) solder have been developed by researchers. The Ni-dopant lead free solder is increasingly used in electronic packages due to its good drop performance. Currently, it lacks the fatigue life model for Ni doped SAC solder. In this paper, thermal cycling test and finite element simulation were conducted for 5 FBGA (Fine pitch BGA) assemblies with Sn-Ag-Cu-Ni (SACN) lead free solder. The thermal fatigue life prediction model was developed for FBGA assemblies with SACN solder by combining experimental and simulation results. The good correlation between predicted and experimental lives was achieved. In addition, the effect of geometry and loading condition on solder joint predicted life was investigated based on the finite element simulation result and the developed life model.

Copper wirebond pull test and reliability characterization with finite element simulation

In this paper, we will compare Cu wire and Au wire behavior during pull test and package reliability test through thermo-mechanical simulation. Relationship between wire pull test and package reliability test, i.e. thermal cycling, is also evaluated in term of die stress underneath the wire bond pad area. A new stress index concept is proposed to characterize the overall die stress level underneath bond pad. Based on this concept, a new method to evaluate Cu pull test limit is established with benchmark to current Au wire standard. The methodology is demonstrated through a Cu wire bonded power package, with the extensive work of process development, reliability test, and stress simulation etc.

Robust power package development with mechanical simulation and reliability validation

Thermo-mechanical reliability is one of the major concerns for electronic packages, especially for power packages operating in extremely harsh environment. As the trends towards high density and function integration, advanced power device becomes more sensitive to environmental stress. Comprehensive study is needed from design, process to test towards robust power package with high reliability. In this paper, we will demonstrate the successful application of simulation in the development of a series of robust leaded power packages. Firstly, finite element analysis(FEA) has been carried out to understand die stress behavior inside the package during assembly and reliability tests, i.e. from die attach, post mold cure, reflow to thermal cycling etc. Then DOE matrix is run to obtain the critical responses to different factors, which leads to guidelines on package design and material selection. A series of robust power packages have been developed with optimized package geometry and bill of materials.

Camera Module Design, Assembly and Test Challenges

With the fast growth of mobile phone market, image sensor and camera module production have skyrocketed in recent years. Semiconductor industry has been put a lot of effort in camera module design, assembly, and test technologies. The technology platform was mainly developed from normal BGA platform. However, camera module is more complex than normal BGA in design, assembly, and test. There were special issues to be taken into consideration. In this paper, challenges of camera module design, assembly and test are discussed. Integrated analysis methodology was addressed for camera module design. Through the analysis of optical and mechanical tilt, module flexibility, loading force during test, reliability test, etc, it is clearly stated that design for assembly, design for test, and design for reliability are very important to create a higher yield product. Integrating theoretical analysis, numerical modeling, and physical test can help to have a fast solution and significantly reduce time to market and time to volume.

Design for Improvement of Drop Impact Performance of IC Packages

Solder joint reliability of IC packages under drop impact becomes a great concern for portable telecommunication devices such as mobile phones and PDAs. It is known that drop impact reliability of lead-free BGA solder joints is a critical challenge. With the development of advanced packaging applications such as system-in-package (SiP), package on package (PoP), embedded die, stacked die BGA, etc, package design is more dependent on modeling as the package structure and failure mechanism are too complicated to be studied. Actual drop test and sample preparation are very expensive and time-consuming, requiring much manpower in measurement and failure analysis, and therefore, there are limited drop test results reported to advise on the package design enhancement, especially for lead-free packages. To avoid long cycle time for package development and expensive reliability testing, design for reliability is necessary in package early design stage. In this paper, various design parameters are studied to understand the effects of solder material, molding compound, substrate, solder mask opening, ball layout, enhancement ball, etc based on a good drop impact model developed in our previous work. A thorough understanding of design variables on impact life of IC packages is obtained. Some factors have significant effects on drop impact life. It is very useful for designer to design a reliable package with such design considerations and guidelines. One point to be noted is that the relative performance of package may be different under board level drop test and thermal cycling test. Therefore, different design guidelines should be considered, depending on application and area of concern.

Enhance TCOB life for wafer level package with a new leadfree solder alloy

Driven by minimized package size, cost as well as performance, wafer level package (WLCSP) is currently one of the fastest growing segments in the semiconductor packaging industry. Not as plastic BGA with a substrate interposer, WLP is a silicon chip directly mounted on printed circuit board (PCB) board. The large CTE(coefficient of thermal expansion) mismatch between silicon and organic leads to very high solder joint stress, which will decrease TCOB(thermal cycling on board) life for solder joints. Thus TCOB life is one of the main challenges on WLCSP, especially with large die. This study is focused on enhancement of TCOB life for WLCSP in the face of increasing die-size requirements. Several WLCSPs with different size are selected as test vehicles. Mechanical simulation has been carried out to understand the TCOB behavior and help to optimize the package design. TCOB test has been done to quantify the real life and to validate the simulation models for current SAC-N solder. To enhance the life margin, especially for large size package, a new Solder SAC-Q has been evaluated. Initial results indicate SAC-Q is showing remarkable TCOB improvement with acceptable drop test performance. Simulation model has been built up to understand the different behavior between SAC-Q and SAC-N. Much lower plastic work in SAC-Q correlates well to its longer life than SAC-N.

Board level drop test simulation using explicit and implicit solvers

Drop test is transient and dynamic in nature. Therefore, explicit solvers such as ANSYS/LS-DYNA and ABQUAS Explicit are employed extensively for the free fall analysis [1-3]. To avoid complexity in modeling contact event, a simplified Input-G method was suggested [4-5]. However, the explicit algorithm suffers from poor numerical stability unless a very fine time increment is used, which means that it is very costly. Implicit solver, on the other hand, is an affordable alternative. Nevertheless, it is not compatible with the direct application of acceleration profile without additional treatment of the boundary conditions [6]. To overcome these numerical obstacles, a dynamic-static modeling approach was introduced where a dynamic analysis is performed to calculate the maximum bending moment of the printed circuit board (PCB), which is used as boundary conditions of the consecutive static analysis of the stress in a detailed local model [7]. This paper investigates the simulation methodologies of board level drop test using both explicit and implicit solvers. It demonstrates that explicit solver could be replaced by implicit solver to model the current industrial specified drop test, which is a moderate transient process, as both solvers gave similar results in terms of peeling stress of solder joints. Moreover, it is possible to model complicate material behavior as well as geometric details, which are extremely difficult for dynamic modeling using explicit solver unless sub-modeling or mass scaling techniques are applied. The results of the numerical analysis are compared and discussed in details.

Wirebondability enhancement for very small die in power packages with dynamic simulation

As microelectronics is moving towards miniaturization, function integration and cost reduction, the device itself is becoming smaller while keeping same or even more functions. Silicon die with area less than 2×2 mm2 is common. This poses challenges for very small die handling and assembly. In another respect, high reliability is required for power packages especially for automotive application. During the development of a new power package module (with 2 devices), wire bondability issue is encountered for the smaller device (1.8×1.9 mm2), while the bigger die is not affected. After continuous effort, root cause analysis is focused on the softening of die attach glue material during high temperature wire bonding process. Finite element modeling is used to understand the dynamic behavior of the module during wirebonding. Both modal analysis and harmonic analysis have been performed. Modeling results confirmed the dynamic effect of glue softening. Results show dynamic response along Y-axis is much higher than that along X-axis, which correlated well with experimental observation. Further optimization has been carried out on package geometry and glue material properties, which leads to assembly guidelines on material selection and process control. Successful product qualification well demonstrated the benefit of numeral simulation for advanced package development.