Roy L. Russo

On a Pin Versus Block Relationship For Partitions of Logic Graphs

Partitions of the set of blocks of a computer logic graph, also called a block graph, into subsets called modules demonstrate that a two-region relationship exists between P, the average number of pins per module, and B, the average number of blocks per module. In the first region, P = KBr, where K is the average number of pins per block and 0.57 ≤ r ≤ 0.75. In the second region, that is, where the number of modules is small (i.e., 1-5), P is less than predicted by the above formula and is given by a more complex relationship. These conclusions resulted from controlled partitioning experiments performed using a computer program to partition four logic graphs varying in size from 500 to 13 000 circuits representing three different computers. The size of a block varied from one NOR circuit in one of the block graphs to a 30-circuit chip in one of the other block graphs.

A Heuristic Procedure for the Partitioning and Mapping of Computer Logic Graphs

A heuristic procedure for partitioning or mapping a set of interconnected blocks into subsets called modules is presented. Each module may be constrained in terms of the number of blocks and/or the number of intermodule connections that it can accommodate. The procedure allows given blocks to be mapped to more than one module in order to reduce the number of modules required if such reduction is desirable. Results obtained from applying the procedure, by means of a computer program, to the partitioning and mapping of computer logic gates into chips and cards are presented.

On the Tradeoff Between Logic Performance and Circuit-to-Pin Ratio for LSI

A key problem in the effective use of large-scale integration is the design and partitioning of computer logic to achieve sufficiently high circuit-to-pin ratios. In this paper a power-law relationship between pins and partitioned circuits is discussed and empirical evidence is presented that implies that the pin requirement is a sensitive function of the performance level of the logic. Two techniques for increasing the circuit-to-pin ratio are discussed. The first is to serialize the interchip transfer of information that results in a degradation in performance of the logic. The second is to encode the information to be transferred so that fewer pins are required but without reducing the performance. The results of experiments using the encoding principle to map a small logic graph onto chips are presented to obtain an indication of the effectiveness of this technique. It is shown that the relationship between circuits and pins when using encoding remains a power law.

ALMS: Automated logic mapping system

ALMS is a set of design automation computer programs which accepts as input a description of a logic design, specifications of modules (e.g., chips, cards, etc.) into which the blocks of the design are to be partitioned or mapped, and some constraints that must be satisfied. It produces as output a documented assignment of the blocks to the modules satisfying the specified constraints. The system algorithms are presented, system features are discussed, program execution times are given and results are presented and compared to manual solutions for the same tasks. Three conclusions are reached. First is that computer programs make it possible to perform partitioning and mapping experiments which were not possible before. Second, for one-level partitions (e.g., logic gates on chips), highly automatic solutions obtained by the program are at least as good as manual solutions and are less costly to obtain. Third, for multi-level partitions (e.g., logic gates on chips on cards) or for mappings, the solutions obtained with the program are again at least as good as manual solutions; further-more, ALMS allows a designer to try more alternatives than he could manually, so that he can trade-off the time and cost of trying additional alternatives against the value of a better solution.

An Example Computer Logic Graph and Its Partitions and Mappings

The purpose of this correspondence is to provide an example computer logic graph and data concerning various partitions and mappings of this graph. This information should be of particular interest to those workers who are developing partitioning and mapping algorithms, since it provides a means to test and compare alternative methods. It should also be of use to those interested in other algorithms (e.g., placement, diagramming, grouping, etc.) for logic graphs.

Workshop Report: Methods of Verification in Design Automation

The 1975 Design Automation Workshop was held at Michigan State University last October 8-10, under the co-sponsorship of the IEEE Computer Society Technical Committees on Design Automation and Fault Tolerant Computing.

Serving a growing community: how D&T began

0740-7475/04/

The logic-to-hardware interface area of design automation

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On pin versus block relationship for partitions of logic circuits

The logic-to-hardware interface area is concerned with the problems of translating a logic description into a high level physical description. The logic description is an interconnection of the primitive circuits, such as Ands, Ors, Nors, Flip-Flops, etc., that are to be used in the physical packages. A high level physical description takes into account, for example, partitioning of the logic into physical packages, but does not include relative placement of the primitive circuits within a package, or pin assignment, wire routing, etc.