Roy M. Jenevein

16-bit vs. 32-bit instructions for pipelined microprocessors

In any stored-program computer system, information is constantly transferred between the memory and the instruction processor. Machine instructions are a major portion of this traffic. Since transfer bandwidth is a limited resource, inefficiency in the encoding of instruction information (low code density) can have definite hardware and performance costs. Starting with a parameterized baseline RISC design, we compare performance for two instruction encodings for the same instruction processing core. One is a variant of DLX, a typical 32-bit RISC instruction set. The other is a 16-bit format which sacrifices some expressive power while retaining essential RISC features. Using optimizing compilers and software simulation, we measure code density and path length for a suite of benchmark programs, relating performance differences to specific instruction set features. We measure time to completion performance while varying memory latency and instruction cache size parameters. The 16-bit format is shown to have significant cost-performance advantages over the 32-bit format under typical memory system performance constraints.

On tolerating faults in naturally redundant algorithms

A class of algorithms suitable for fault-tolerant execution in multiprocessor systems by exploiting the existing embedded redundancy in the problem variables is characterized. Because of this unique property, no extra computations need be superimposed on the algorithm in order to provide redundancy for fault recovery, as well as fault detection in some cases. A forward recovery scheme is thus used with very low time overhead. The method is applied to the implementation of two iterative algorithms: solution of Laplace equations by Jacobis method and the calculation of the invariant distribution of a Markov chain. Experiments show less than 15% performance degradation for significant problem instances in fault-free situations, and as low as 2.43% in some cases. The extra computation time needed for locating and recovering from a detected fault does not exceed the time necessary to execute a single iteration. The fault-detection procedures provide fault coverage close to 100% for faults causing errors that affect the correctness of the computations.<<ETX>>

Nest: a nested-predicate scheme for fault tolerance

Introduces a nested-predicate scheme for fault tolerance, called Nest. Nest provides a formal comprehensive model for fault-tolerant parallel algorithms and a general methodology for designing reliable applications for multiprocessor systems. The model relies on the formalization of concepts for fault tolerance by means of three nested system predicates and on properties ruling their interrelationships. This rigorous framework facilitates the study of the specific properties that enable an algorithm to tolerate faults. The consequence of that is the outline of systematic design techniques that can be used to add fault tolerance properties to algorithms while preserving their functional characteristics. >

The KYKLOS multicomputer network: interconnection strategies, properties, and applications

A tree-based interconnection architecture (called KYKLOS) for multicomputer systems is proposed. While the general form of the topology consists of multiple m-ary trees sharing a common set of leaf nodes, the focus is on the dual-tree case. One version of the dual-tree KYKLOS involves a bottom tree where the ordering of descendants of nodes at every level is an m-way shuffle. This architecture provides fault tolerance and vastly improved properties over the simple double tree while retaining the simplicity and low fan-out of the m-ary tree. Different routing strategies are presented and network properties as a function of routing strategy are investigated. The O(N/sup 2/) congestion at the root of the m-ary tree is reduced to O(N/sup 1.5/) while average normalized communication latencies are decreased. Applications of this architecture to facilitate parallel input/output (I/O) access and parallel processing of database operations such as the relational join are studied. >

A Parallel Multi-Stage I/O Architecture with Self-Managing Disk Cache ForDatabase Management Applications

This paper first defines and describes a highly parallel external data handling system and then shows how the capabilities of the system can be used to implement a high performance relational data base machine. The elements of the system architecture are an interconnection network which implements both packet routing and circuit switching and which implements data organization functions such as indexing and sort merge and an intelligent memory unit with a self-managing cache which implements associative search and capabilities for application of filtering operations on data streaming to and from storage.

Design of a Hyperkyklos-based Multiprocessor Architecture forHigh-performance Join Operations

The traffic characteristics of various distributed join algorithms on the Hypercube are analyzed. It is shown that, regardless of which join strategy is employed, the network bandwidth requirements of the computation and collection phases are radically different. This imbalance prevents these two phases from being pipelined (overlapped). To alleviate this problem, the HyperKYKLOS Network is proposed. The topology of this network is defined and a brief description of the I/O nodes presently under construction is included.

Traffic analysis of rectangular SW-banyan networks

This paper describes an algorithm to route packets in Rectangular SW-Banyans. A packet switching scheme is modelled on single and double sided SW-Banyans and the results presented. Effects of queue lengths and processor configurations on performance are studied. Prevention of deadlocks in the network is discussed.

Space/Time Overhead Analysis and Experiments with Techniques for Fault Tolerance

This paper presents the results of practical experiments, implemented on a multiprocessor platform, with several techniques for fault tolerance. We analyze and contrast the time and space overheads incurred by each technique. Three iterative algorithms were used in the experiments: solution of Laplace equations, the calculation of the invariant distribution of Markov chains, and the solution of systems of linear equations. Fault-tolerant versions of these algorithms were implemented with two general techniques for fault tolerance (triplication with voting, and checkpointing and rollback) and three application-specific techniques for fault tolerance (self stabilization, algorithm-based fault tolerance, and natural redundancy). The experimental results show that the approach based on natural redundancy, for applications possessing that property, presents the most attractive cost/benefit ratio when only single faults are likely to occur. The execution of the three algorithms implemented with this technique required less than a 15% time redundancy for significantly sized problems in fault-free situations, only one extra iteration to recover from a fault, and no extra processors. These capabilities are ideal for critical applications that must deliver reliable and timely service. Surprisingly, time overheads for some other methods were much higher than expected.

SDL specification and verification of a distributed access generic optical network interface for SMDS networks

This paper presents the design and specification of a BISDN user-to-network interface (UNI) named DRAGON (Distributed Access Generic Optical Network) for SMDS networks. The UNI allows clusters of nodes to be connected to an SMDS network via fiber-optic lines. The capacity of each line is shared by all the nodes in the cluster to make more efficient use of bandwidth. We constructed an extended finite state model (EFSM) of the DRAGON using ITU standard Specification and Description Language (SDL). The model was simulated and validated using the SDT 3.02 toolset from Telelogic. An extensive set of simulations were conducted to ascertain correct logical behavior. The model was then independently verified using two different algorithms: bit-state and random walk. The results showed that the design was verified to a high degree of coverage.

A distributed access generic optical network interface for SMDS networks

This paper presents the design and analysis of a BISDN user-to-network interface (UNI) for SMDS networks. The UNI allows clusters of nodes to be connected to an SMDS switching network via fiber-optic lines. The capacity of the line is shared by all the nodes in the cluster, thus making more efficient use of its bandwidth. Within each cluster, transmissions are scheduled on first-come-first-served (FCFS) order of message arrivals, by considering a globally distributed queue. A novel scheme is proposed for controlling access to the fiber-optic transmission network by using two separate subnetworks called the reservation channel and the reservation ring. Slot reservations are made independently from the message transmissions. VHDL was used to construct an RTL model of the UNI. Accurate timing simulations were performed on a cluster of three nodes, and the model was validated using concurrent video and data traffic. Clusters of different sizes were modelled and simulated. Using integrated VBR video and Ethernet traffic traces from Bellcore, a number of quality-of-service (QOS) parameters were measured and are presented.