Rüdiger Schmolke

Morphology Change of Artificial Crystal Originated Particles, and the Effect on Gate Oxide Integrity

The surface morphology and gate oxide integrity was examined on wafers containing Artificial Crystal Originated Particles. The wafers were subjected to heat treatments, epitaxial silicon deposition and polishing. All treatments except polishing result in a significant defect smoothening, or even in complete defect annihilation. On these wafers, the defects no longer degrade the gate oxide integrity. Polishing only smoothes convex defect edges, leading to a reduction of the leakage current with positive gate bias. The breakdown voltage remains nearly unaltered, implying that it is determined by the concave tip of the defect.

Observation of Extremely Low Defect Densities in Silicon Wafers

Defects in p- polished silicon wafers originating from Czochralski (Cz)-pulled crystals are commonly delineated by hot SC1 treatment with immersion times in the range from about 20 min to 4 h corresponding to silicon removals of 20 nm to 200 nm. This procedure is no longer applicable for wafers with defect densities that are orders of magnitude lower than in Cz p- wafers due to their very low count rates. However, a low defect density, such as in homoepitaxial silicon layers, can be investigated by sequentially treating wafers in hot SC1 solution several times so that the overall duration of the preparation is on the order of twenty hours resulting in a silicon removal of about 1 µm. Defects delineated by hot SC1 etching can, in addition, be investigated with an atomic force microscope. In the case of homoepitaxial silicon layers, these defects are identified as single as well as dual pits with a morphology characteristic of so-called crystal originated particles (COPs) as observed on p- Cz wafers. These COPs are related to voids generated by vacancy agglomeration in the growing ingot. The morphology of the delineated defects indicates that such voids exist in homoepitaxial layers as well, which is supported by the fact that the temperature range relevant for void formation in p- Cz silicon crystals is also used in silicon homoepitaxial growth. The oxygen backpressure during homoepitaxial silicon growth is negligible. Thus, formation of voids in the epitaxial layer is not influenced by oxygen, specifically when an oxygen-free silicon substrate, such as a wafer cut from a floating-zone (FZ) crystal, is used. However, not only single but also dual-pit COPs are observed on such epitaxial layers after delineation, which questions assumptions and models in the literature attributing the formation of multiple voids in p- Cz silicon crystals to the role of oxygen.

Fabrication and Characterization of Artificial Crystal Originated Particles

Crystal Originated Particles on silicon substrates were imitated by anisotropic etching of pits in the wafer surface. The effect of these artificial defects on the gate oxide in Metal-Oxide-Semiconductor devices was studied. The results show a combined effect of local oxide thinning and electric field distortion on the electrical characteristics of the gate oxide.

Requirements of measurement equipment for silicon wafers

Measurement equipment for geometry, shape, surface finish of bare silicon wafers are highly sensitive tools operating partly at their capability limits. This results in performance problems which have to be solved if such equipment is to be of benefit for developing future generations of silicon wafers with specifications according to the SIA roadmap for semiconductors. The instruments for measuring the mentioned parameter belong to a class of tools the output of which is strongly influenced by their bandwidth. The requirements for future measurement equipment for specific measurement tasks as well as for generic capabilities which have to be met by all tools operating in a production ambient are outlined.