Ruhan Conceicao

Hardware design for the 32×32 IDCT of the HEVC video coding standard

This paper is focused in the inverse transforms defined in the video coding standard HEVC - High Efficiency Video Coding. The transforms stage is one of the innovations proposed by HEVC since it allows the use of the biggest number of transforms sizes (four) and also the biggest transform sizes (till 32×32) when compared with previous standards. The inverse DCT is performed by the video encoder and decoder as well. This paper presents an efficient hardware design for the 32×32 HEVC IDCT based on the separability principle. The hardware design was planned to reach real time processing (at least 30 frames per second) for high resolution videos, exploiting a high parallelism level (32 samples consumed per clock cycle). The architecture was also planned to reach a low latency and a low cost, then it was designed in a purely combinational way and using a multiplierless approach. The synthesis process was targeted to an Altera Stratix IV FPGA. The synthesis results show that the designed architecture is capable to process more than 30 QFHD frames (3840×2160 pixels) per second, with a latency of 33 clock cycles.

Complexity reduction for 3D-HEVC depth map coding based on early Skip and early DIS scheme

This paper presents a novel early Skip/DIS mode decision for 3D-HEVC depth encoding which aims at reducing the complexity effort of this process. The proposed solution is based on an adaptive threshold model, which takes into consideration the occurrence rate of both Skip and DIS modes. Occurrence analysis showed that the lower is the Skip and DIS Rate-Distortion cost, the higher is the probability of these modes being chosen. Furthermore, software evaluations showed that the proposed early Skip/DIS scheme is capable of reducing the depth coder complexity in 24.4% for a target hit rate of 99%, and in 33.7% for a target hit rate of 95%, leading to a negligible coding efficiency penalty in both scenarios.

Power efficient and high troughtput multi-size IDCT targeting UHD HEVC decoders

This paper is focused on the inverse transforms defined in the HEVC (High Efficiency Video Coding) standard. The HEVC standard allows the use of four transform sizes, including novel transforms applied over bigger block sizes (16×16 and 32×32). The hardware architecture presented in this paper was planned to reach real-time processing (at 30 frames per second) for ultra-higher solution videos, exploiting high level of parallelism. As a secondary goal, the architecture was also planned to reach low cost in terms of hardware consumption and power dissipation. Thus, the architecture was designed in a purely combinational way, using a multiplierless approach and employing an optimization algorithm through operations reuse and sub-expressions sharing. The synthesis targeted an Altera Stratix V FPGA and ASIC 90nm standard-cells technology. The synthesis results show that the designed architecture has the best performance results among all related works, being able to achieve real-time decoding for UHD videos (7680×4320 pixels) with a power consumption from 33.8mW to 339.2 mW.

Sample adaptive offset filter hardware design for HEVC encoder

This work presents a hardware design for the Sample Adaptive Offset filter, which is an innovation brought by the new video coding standard HEVC. The architectures focus on the encoder side and include both classification methods used in SAO, the Band Offset and Edge Offset, and also the statistical calculations for the offset generation. The proposed architectures feature two sample buffers, classification units for both SAO types and the statistical collection unit. The architectures were described in VHDL and synthesized to an Altera Stratix V FPGA. The synthesis results show that the proposed architectures achieve 364MHz and are capable to process 44 QFHD (3840×2160) frames per second using 8,040 ALUTs of the target device hardware resources.

Complexity reduction of 3D-HEVC based on depth analysis for background and ROI classification

The 3D extension of the High Efficiency Video Coding (HEVC) standard achieves large compression rates thanks to the addition of several tools to encode multiview and depth information on top of those available in HEVC. The use of such tools incur in a very large computational demand, which can be a serious problem in power and computationally-constrained devices and applications. However, not all information contained in an image is fundamental to the viewer, so that different levels of computational effort can be employed when encoding different image regions. The Region of Interest (ROI) concept is used in this work to classify each Coding Unit (CU) as foreground, heterogeneous background and homogeneous background. Then, a simplified encoding process is employed in those regions classified as homogeneous background, terminating earlier the partitioning process in texture CUs, while still still performing the regular decisions in areas classified as ROI. Experimental results show an average reduction of 22.6% in computational complexity for texture coding with negligible or non-perceived image quality degradation.

Hardware design of fast HEVC 2-D IDCT targeting real-time UHD 4K applications

This paper presented a hardware design of an 4-points IDCT inverse transform module defined in the newest video coding standard, the HEVC. This work proposes a simpler way to calculate the HEVC 4-points IDCT. This approach focuses in the occurrence of special cases where the result can be calculated without the full IDCT processing. These simplifications reduced about 87.5% the number of 1-D IDCT calculations in the whole 2-D IDCT process, with an increasing of 0.4% in BD-Rate. The focus of the developed hardware design is to achieve real-time processing for UHD 4K (3840×2160 pixels) video sequences, with low hardware resources use and high performance. The architecture was implemented targeting a Cyclone V FPGA device. Synthesis results show that the designed hardware is capable to process UHD 4K videos in real time, processing up to 100 UHD 4K frames per second. Moreover, compared to the IDCT hardware design, without the proposed approach, the reduction in terms of hardware resources consumption achieves 72.3%.

Low-power and high-throughput hardware design for the 3D-HEVC depth intra skip

This paper presents a low-power and high-throughput hardware design for the 3D-HEVC (Three Dimensional High Efficiency Video Coding) Depth Intra Skip coding tool. A strategy to reduce the computational effort was employed based on an analysis using the 3D-HEVC reference software. The proposed strategy consists of replacing the SVDC (Synthesized View Distortion Change) for the SAD (Sum of Absolute Differences) as the similarity criterion. This way, the number of arithmetic operations related with the similarity criterion is reduced over 71%, and a rendering process is avoided at the cost of only 0.21% increase in the BD-Rate. The hardware was described in VHDL and synthesized for ASIC technology. The synthesis results for the 45nm Nangate standard cells demonstrate that the architecture can process 60 UHD 2160p frames per second (five views) with a power dissipation of 19.57mW.

Rate and Complexity-Aware Coding Scheme for Fixed-Camera Videos Based on Region-of-Interest Detection

This paper presents a rate and complexity-aware coding scheme for fixed-camera videos that are designed to improve image quality in Regions of Interest (ROI) by prioritizing the encoding of such regions through the use of a modified mode decision equation. ROIs are defined in this work as faces, with the application of a face detection algorithm. Background Images (BGI) are also detected with the aim of reducing bitrate in coding blocks belonging to these areas. Finally, the proposed scheme also applies an early decision method intending to reduce coding time. Experimental results show that the proposed scheme is capable of improving the image quality in 0.99 dB in ROIs, reaching an improvement of 1.16 dB in the best case. Also, the scheme achieves an encoding time reduction of up to 55% (about 5.5%, on average) with unexpressive variations in the required bitrate.

Video Quality Assessment of Early SKIP/DIS for 3D-HEVC Complexity Reduction

This paper presents a quality analysis of 3D videos encoded with the 3D extension of the High Efficiency Video Coding (HEVC) standard, 3D-HEVC, using the Early Skip/DIS heuristic to reduce complexity. In addition to comparing the heuristic from a quality point of view, the analyses were performed with objective and subjective methodologies with the goal of comparing the reliability of the metrics. Three metrics were employed in the objective evaluation: Peak Signal-to-Noise Ratio (PSNR), Structural Similarity (SSIM) e Most Apparent Distortion (MAD). The subjective analyses considered the Mean Opinion Score (MOS) metric using double stimulus. The evaluation results demonstrated that the Early Skip/DIS solution has no significant impact in image quality in comparison with videos encoded with the unmodified 3D-HEVC reference encoder.

Rate-distortion-complexity analysis for prediction unit modes in 3D-HEVC depth coding

3D-HEVC achieves significant compression efficiency thanks to the addition of several tools and features for multiview and 3D video content on top of those already available in HEVC. However, such gains come at the cost of large increases in the encoding computational complexity, which is a problem for computationally and battery-constrained devices. As the use of each tool or feature yields different compression efficiency, those that do not contribute significantly should be the first to be disabled in a complexity-constrained system with limited computational resources. Thus, this paper presents two major analyses on the use of Prediction Unit (PU) modes in 3D-HEVC: a preliminary, statistical study and a Rate-Distortion-Complexity (RDC) analysis. The first study observed the occurrence of asymmetric and rectangular PU modes in depth maps, while the RDC analysis evaluated the impact caused by the deactivation of the least used modes during the encoding of depth maps, based on the results found in the preliminary study. Experimental results have shown that a computational complexity reduction of 9% can be achieved with a negligible rate-distortion penalty (0.1%) if the least used modes are disabled.