Vladimir Afonso

Low cost and high throughput FME interpolation for the HEVC emerging video coding standard

The new demands for high resolution digital video applications are pushing the development of new techniques in the video coding area. This paper presents the hardware design of the sub-pixel interpolator for the Fractional Motion Estimation algorithm defined by the HEVC emerging standard. Based on evaluations using the HEVC reference software, a strategy was defined to be used in the architectural design. The designed architecture was described in VHDL and synthesized for Altera FPGAs. The hardware designed presents interesting results in terms of performance, being able to process QFHD videos (3840×2160 pixels) in real time.

HEVC Fractional Motion Estimation complexity reduction for real-time applications

This paper presents a compression analysis about the High Efficiency Video Coding (HEVC) standard targeting a computational effort reduction at the scope of the motion estimation (ME). Restricting the Prediction Units (PUs) - among a total of 24 sizes - to the 4 square-shaped sizes in the HEVC interframes prediction, it is possible to reduce in 74% the number of operations at the cost of 4% increase in the bit-rate, considering the Y-BD-Rate metric. Based on this evaluation, a simple hardware architecture is proposed to implement the Sum of Absolute Differences (SAD) used in the Fractional Motion Estimation (FME). The proposed architecture is able to calculate SAD with a rate of 30 Full HD (1920×1080) frames per second, requiring a frequency of 1.17GHz. It represents a 63% frequency reduction compared to a scenario where all 24 PU sizes are evaluated.

Memory-Aware and High-Throughput Hardware Design for the HEVC Fractional Motion Estimation

This paper presents a hardware design for the Fractional Motion Estimation (FME) of the High Efficiency Video Coding (HEVC) standard. The solution designed in this work uses a scheme to reduce the number of accesses to the reference frames stored in the external memory in up to 49.22%. A strategy to reduce the computational effort is also used. This strategy consists in using only the four square-shaped Prediction Unit (PU) sizes rather than using all the 24 possible PU sizes. This approach reduces the total encoding time in about 59%, with a bit-rate increase of only 4% for the same image quality. The hardware design was described in VHDL and synthesized for FPGA and ASIC technologies. The synthesis results for TSMC 65nm standard cells demonstrate that the developed design is able to process UHD 2160p videos at 60 frames per second (fps), reducing the required hardware resources in about five times when compared with the main related work.

A multi-standard interpolation hardware solution for H.264 and HEVC

Attending real-time constraints in video coding systems represents a big challenge for nowadays systems, especially for high definition videos at mobile systems. The Fractional Motion Estimation (FME) and Motion Compensation (MC) are responsible for a large share of processing effort in both state-of-the-art video coding standards, the High Efficiency Video Coding (HEVC), and its predecessor, the H.264. This work proposes a multi-standard hardware solution for the fractional sample interpolation used in FME/MC processing of the HEVC and H.264 standards. The hardware design is composed of four IP (Intellectual Property) cores able to process 1080p@60fps videos independently. The whole architecture can process 2160p@60fps with 80.69mW, considering bi-prediction.

High throughput hardware design for the HEVC Fractional Motion Estimation Interpolation Unit

This paper presents a hardware design for the Fractional Motion Estimation (FME) Interpolation Unit compatible with the High Efficiency Video Coding (HEVC) standard. The proposed architecture was designed to consider fixed 16×16 Prediction Unit (PU) size in order to drastically reduce the computational effort. This decision was made taking into account several evaluations, using the HEVC Reference Software, to find out the number of occurrences of each PU size and their coding efficiency impact. The designed architecture was described in VHDL and synthesized to an Altera Stratix III FPGA. The results show that the designed architecture is able to process QFHD videos at 60 frames per second with a 353.8 MHz clock frequency.

A multi-standard interpolation filter for motion compensated prediction on high definition videos

This paper proposes a hardware design for a multi-standard interpolation filter for the motion compensated prediction targeting H.264/AVC and HEVC video coding standards, which can be applied for Fractional Motion Estimation (FME) and Motion Compensation (MC) steps. In this paper it is introduced the fractional samples generation according to these standards, and the differences between them are highlighted. After that, an analysis was made to merge the interpolation filters of both standards, so an optimized hardware design could be proposed. The developed hardware architecture was described in VHDL and synthesized for FPGA and ASIC technologies. The hardware results for the TSMC 65nm ASIC technologies report 5.7K gates with a power consumption of 2.69mW when running at 806.45MHz.

Simplified HEVC FME Interpolation Unit Targeting a Low Cost and High Throughput Hardware Design

Summary form only given. The new demands for high resolution digital video applications are pushing the development of new techniques in the video coding area. This paper presents a simplified version of the original Fractional Motion Estimation (FME) algorithm defined by the HEVC emerging video coding standard targeting a low cost and high throughput hardware design. Based on evaluations using the HEVC Model (HM), the HEVC reference software, a simplification strategy was defined to be used in the hardware design, drastically reducing the HEVC complexity, but with some losses in terms of compression rates and quality. The used strategy considered the use of only the most used PU size in the Motion Estimation process, avoiding the evaluation of the 24 PU sizes defined in the HEVC and avoiding also the RDO decision process. This expressively reduces the ME complexity and causes a bit-rate loss lower than 13.18% and a quality loss lower than 0.45dB. Even with the proposed simplification, the proposed solution is fully compliant with the current version of the HEVC standard. The FME interpolation was also simplified targeting the hardware design through some algebraic manipulations, converting multiplications in shift-adds and sharing sub-expressions. The simplified FME interpolator was designed in hardware and the results showed a low use of hardware resources and a processing rate high enough to process QFHD videos (3840x2160 pixels) in real time.

Low-power and high-throughput hardware design for the 3D-HEVC depth intra skip

This paper presents a low-power and high-throughput hardware design for the 3D-HEVC (Three Dimensional High Efficiency Video Coding) Depth Intra Skip coding tool. A strategy to reduce the computational effort was employed based on an analysis using the 3D-HEVC reference software. The proposed strategy consists of replacing the SVDC (Synthesized View Distortion Change) for the SAD (Sum of Absolute Differences) as the similarity criterion. This way, the number of arithmetic operations related with the similarity criterion is reduced over 71%, and a rendering process is avoided at the cost of only 0.21% increase in the BD-Rate. The hardware was described in VHDL and synthesized for ASIC technology. The synthesis results for the 45nm Nangate standard cells demonstrate that the architecture can process 60 UHD 2160p frames per second (five views) with a power dissipation of 19.57mW.

An efficient sub-sample interpolator hardware for VP9-10 standards

This paper presents a hardware design for the sub-sample interpolator used in FME (Fractional Motion Estimation) and MC (Motion Compensation) stages according to the VP9 and VP10 video-coding standards. The proposed architecture is able to save hardware resources through an optimized-filter organization whereas reaching high-throughput and low-power dissipation. The hardware design was described in Verilog and synthesized for ASIC technology. The synthesis results were generated for 45nm Nangate standard cells and demonstrate that the developed architecture is able to process 2160p@60fps videos with a power dissipation of 2.34mW focusing on a VP9-10 decoder.