Ruijing Shen

Fundamentals of Statistical Analysis

To make this book self-contained, this chapter will review relevant mathematical concepts used in this book. We first review basic probability and statistical concepts used in this book. Then we introduce mathematic notations for statistical processes with multiple variable and variable reduction methods. We will then go through some statistical analysis approaches such as the MC method and the spectral stochastic method. Finally, we will discuss some fast techniques to compute some of random variables with log-normal distributions.

Linear Statistical Leakage Analysis by Virtual Grid-Based Modeling

When the spatial correlation is weak, existing general approaches mentioned in Chaps. 3 and 4 do not work well as the number of correlated variables cannot be reduced too much. Recently, an efficient method was proposed [200] to address this problem. The method is based on simplified gate leakage models and formulates the major computation tasks into matrix–vector multiplications via Taylor’s expansion. It then applies fast numerical methods like the fast multipole method or the precorrected fast Fourier transformation (FFT) method to compute the multiplication. However, this method assumes the gate-level leakage currents are purely log-normal, and the chip-level leakage is also approximated by log-normal distribution, which is not the case as we will show in the chapter. Also it can only give the mean and variances, not the complete distribution of the leakage powers.

Incremental Extraction of Variational Capacitance

Since the interconnect length and cross area are at different scales, the variational capacitance extraction is quite different between the on-chip[209, 205, 21] and the off-chip[210, 34]. The on-chip interconnect variation from the geometrical parameters, such as width length of one panel and distance between two panels, is more dominant[209, 21] than the rough surface effect seen from the off-chip package trace. However, it is unknown how to leverage the stochastic process variation into the matrix-vector product (MVP) by fast multipole method (FMM)[210, 209, 205, 21, 34]. Similar to deal with the stochastic analog mismatch for transistors[133], a cost-efficient full-chip extraction needs to explore an explicit relation between the stochastic variation and the geometrical parameter such that the electrical property can show an explicit dependence on geometrical parameters. Moreover, the expansion by OPC with different collocation schemes[196, 187, 209, 21, 34] always results in an augmented and dense system equation. This significantly increases the complexity when dealing with a large-scale problem. The according GMRES thereby needs to be designed in an incremental fashion to consider the update from the process variation. As a result, a scalable extraction algorithm similar to [118, 77, 163] is required to consider the process variation with the new MVP and GMRES developed accordingly as well.

Voltage Binning Technique for Yield Optimization

Process-induced variability has huge impacts on the circuit performance and yield in the nanometer VLSI technologies [71]. Indeed, the characteristics of devices and interconnects are prone to increasing process variability as device geometries get close to the size of atoms. The yield loss from process fluctuations is expected to increase as the transistor size scaling down. As a result, improving yields considering the process variations is critical to mitigate the huge impacts from process uncertainties.

Traditional Statistical Leakage Power Analysis Methods

Process-induced variability has huge impact on the circuit performance in the sub-90 nm VLSI technologies [120]. This is the particular case for leakage power, which has increased dramatically with the technology scaling and is becoming the dominant chip power dissipation [71].

Statistical Dynamic Power Estimation Techniques

It is well accepted that the process-induced variability has huge impacts on the circuit performance in the sub-90 nm VLSI technologies. The variational consideration of process has to be assessed in various VLSI design steps to ensure robust circuit design. Process variations consist of both inter-die ones, which affect all the devices on the same chip in the same way, and intra-die ones, which represent variations of parameters within the same chip. These include spatially correlated variations and purely independent or uncorrelated variations. Spatial correlation describes the phenomenon that devices close to each other are more likely to have similar characteristics than when they are far apart. It was shown that variations in the practical chips in nanometer range are spatially correlated [195]. Simple assumption of independence for involved random variables can lead to significant errors.

Statistical Power Grid Analysis by Stochastic Extended Krylov Subspace Method

In this chapter, we present a stochastic method for analyzing the voltage drop variations of on-chip power grid networks with log-normal leakage current variations, which is called StoEKS and which still applies the spectral-stochastic-method to solve for the variational responses. But different from the existing spectral-stochastic-based simulation method, the EKS method [191, 177] is employed to compute variational responses using the augmented matrices consisting of the coefficients of Hermite polynomials. Our work is inspired by recent spectral-stochastic-based model order reduction method 2[214]. We apply this work to the variational analysis of on-chip power grid networks considering the variational leakage currents with the log-normal distribution.

Statistical Power Grid Analysis by Variational Subspace Method

In this chapter, we present a novel scalable statistical simulation approach for large power grid network analysis considering process variations[92]. The new algorithm is very scalable for large networks with a large number of random variables. Our work is inspired by the recent work on variational model order reduction using fast balanced truncation method (called variational Poor man’s TBR method, or varPMTBR [134]). The new method, called varETBR, is based on the recently proposed ETBR method[9394]. To consider the variational parameters, we extend the concept of response Gramian, which was used in ETBR to compute the reduction projection subspace, to the variational response Gramian. Then MC-based numerical integration is employed to multiple-dimensional integrals. Different from traditional reduction approaches, varETBR calculates the variational response Gramians, considering both system and input source variations, to generate the projection subspace. In this way, much more efficient reduction can be performed for interconnects with massive terminals like power grid networks[177]. Furthermore, the new method is based on the globally more accurate balanced truncation reduction method instead of the less accurate Krylov subspace method as in EKS/IEKS[191,89].

Statistical Leakage Power Analysis by Spectral Stochastic Method

In this chapter, we present a gate-based general full-chip leakage modeling and analysis method [157]. The gate-based method starts with the process variational parameters such as the channel length, δL, and gate oxide thickness, δT ox, and it can derive the full-chip leakage current I leak in terms of those variables directly (or their corresponding transformed variables). Unlike existing grid-based methods, which trade the accuracy for speedup, the presented method is gate-based method and uses principal component analysis (PCA) to reduce the number of variables with much less accuracy loss, assuming that the geometrical variables are Gaussian. For non-Gaussian variables, independent component analysis (ICA) [68] can be used. The presented method considers both inter-die and intra-die variations, and it can work with various spatial correlations. The presented method becomes linear under strong spatial correlations. Unlike the existing approaches [13, 65], the presented method does not make any assumptions about the distributions of final total leakage currents for both gates and chips and does not require any grid-based partitioning of the chip. Compared with [5], the presented method applies a more efficient multidimensional numerical quadrature method (vs. reduced number of variables using interproduction via the moment matching), considers more accurate leakage models, and presents more comprehensive comparisons with other methods.

Stochastic Analog Mismatch Analysis

For sub-90 nm technologies, mismatch in transistor is one of the primary obstacles to reach a high yield rate for analog designs. For example, mismatch of CMOS devices nearly doubles for every process generation less than 90 nm [80, 104] due to an inverse-square-root-law dependence with the transistor area.