Ruoh-Huey Uang

Design of nanowire anisotropic conductive film for ultra-fine pitch flip chip interconnection

As the prediction that the I/O pitch will decrease from 60 um in 2004 to 20 um beyond 2010 by ITRS roadmap, flip chip interconnection by traditional ACF containing conductive particles with micro-meter size will face more and more challenges. One of many possible solutions is using high aspect-ratio metal posts or flake instead of conductive particles for electrical interconnection between chip and substrate. But this interconnection by metal posts is less reliable compared with elastic conductive particles. Therefore we develop a new type of conductive film composed of nanowires and polymer. Unlike some other composed material by blending nanowires, tubes, powders in polymer, the arrangement of nanowires in polymer is highly ordered in X, Y, and Z direction for anisotropic conductance. In order to achieve high reliability performance of this novel package, the structure design of flip chip package constructed by nanowires/polymer conductive film was evaluated by stress simulation and related D.O.E analysis. In this research, series of finite element models were established based on the D.O.E. (design of experiment) matrix. The four factors including thickness of nanowires/polymer composed film, volume ratio of nanowires in nanowires/polymer composed film, CTE and Youngs modulus of polymer were used in this D.O.E. matrix. The full factorial DOE matrix was applied to optimize the response of peeling stress. These results indicated that volume ratio of nanowires was the major factor. The other important factor was film thickness. Besides the above stress analysis, we also demonstrated the production of nanowires/polymer composed film. Now we can obtain the silver nanowires/polyimide composed films with diameter of nanowire about 200nm and maximum film thickness up to 50 um. The X-Y insulation resistance is about 4~6 GOmega and Z-direction resistance including the trace resistance (3mm length) is less than 0.2Omega

Fabrication of Nanowire Anisotropic Conductive Film for Ultra-Fine Pitch Flip Chip Interconnection

As the prediction that the I/O pitch will decrease from 60 um in 2004 to 20 um beyond 2010 by ITRS roadmap, flip chip interconnection by traditional ACF containing conductive particles with micro-meter size will face more and more challenge. One of many possible solutions is using high aspect-ratio metal posts or flake instead of conductive particles for electrical interconnection between chip and substrate. But this interconnection by metal posts is less reliable compared with elastic conductive particles. Therefore we develop a new type of conductive film composite of nanowires and polymer. Unlike some other composed material by blending nanowires, tubes, powders in polymer, the arrangement of nanowires in polymer is highly ordered in X, Y, and Z direction for anisotropic conductance. In this paper, we used AAO templates to obtain silver and cobalt nanowires array by electrodeposition. And then low viscous PI were spread over and filled into the gaps of nanowires array after surface treatment. The bi-metallic Ag/Co nanowires could keep parallel during fabrication by magnetic interaction between cobalt and applied magnetic field. Now we can obtain the silver and cobalt nanwires/polyimide composite films with diameter of nanowire about 200nm and maximum film thickness up to 50 um. The X-Y insulation resistance is about 4~6 GΩ and Z-direction resistance including the trace resistance (3mm length) is less than 0.2Ω. Besides, we also demonstrated the evaluation of this nanowire composite film by stress simulation. In this study, series of finite element models were established based on D.O.E. and the response of peeling stress was in a range from approximated 10 MPa to 20 MPa when the modulus and CTE of polymer was assumed as 3 GPa and 50 ppm.

On the Thermal–Mechanical Behaviors of a Novel Nanowire-Based Anisotropic Conductive Film Technology

Extensive understanding and management of the thermal-mechanical characteristics of novel packaging designs during the bonding process are indispensable to the realization of the technologies. Thus, this paper attempts to explore the bonding process-induced thermal-mechanical behaviors of an advanced flip chip (FC) electronic packaging. FC packaging employs a novel anisotropic conductive film, which is a thin composite film composed of polymer matrix and thousands of millions of highly oriented, 1-D silver (Ag) nanowires on the scale of 200 nanometers in diameter. For carrying out the process simulation, a process-dependent finite element (FE) simulation methodology that integrates both thermal and nonlinear contact FE analyses and a special meshing scheme is applied. The material properties of the nanoscale Ag wires are first explored using molecular dynamics (MD) simulations. By the characterized material properties of the Ag nanowires, the effective material properties of the composite film are derived through two theoretical approaches: 1) the rule-of-mixture (ROM) technique and 2) the proposed FE method-based approach. The predicted results by these two approaches are extensively compared with each other to examine the feasibility of using the widely used ROM technique for such cases. In addition, the validity of the proposed process-dependent FE simulation methodology is also confirmed through three experiments: 1) micro-thermocouple measurement of temperature; 2) Twyman-Green Moire interferometry measurement of out-of-plane deformations; and 3) portable engineering Moire interferometry measurement of in-plane deformations. Throughout the investigation, the effectiveness of the novel interconnect technology is demonstrated. Good agreement with the experiments is also obtained. It is found that the technology may ensure good electrical performance and structural integrity, not only at room temperature but even at elevated temperature, based on its substantial contact stresses but minor peeling stresses on the bonding line, together with a moderate, process-induced warpage on the substrate.

The reliability performance of low cost bumping on aluminum and copper wafer

A low cost bumping technology for semiconductor chips is described here using electroless Ni/Au plating for under bump metallurgy (UBM) formation, instead of traditional processes involving sputtering, photolithography, and etching which require a great deal of expensive equipment. Higher throughput and lower cost can be achieved if we combine electroless Ni/Au technology and stencil solder printing technology. Low cost bumping technology has been successfully developed on Al wafers. The results of reliability tests, such as high temperature storage, temperature cycling and temperature-humidity storage, show that solder bumps with electroless Ni/Au as UBM exhibit good reliability and are suitable for flip-chip applications. In addition to electroless Ni/Au plating on Al pads, the development of low cost bumping on Cu wafers is also presented in this paper. The performance of Ni/Au bumps on copper, such as morphology and shear strength, is superior to that on Al pads. The reliability tests of low cost solder bumps were also performed on dummy copper wafers that consist of sputtered Cu and PI passivation. Comparisons were also made of the reliability performance of low cost solder bumps on aluminum and copper pads in this paper.

Fine pitch low-cost bumping for flip chip technology

In this paper, a low-cost and fine pitch bumping process by electroless Ni-Au bumping for the UBM (under bump metallurgy) and stencil printing for the solder bump is studied. The solder bumps are made of eutectic SnPb. The pitches of the solder bumps range from 300 /spl mu/m to 200 /spl mu/m for various stencil openings from 210 /spl mu/m to 125 /spl mu/m. The regular bump height is 90 /spl mu/m for the 200 /spl mu/m pitch. The pad opening size is also controlled as a variable. The kinetics of zincating on an Si-Cu surface and on an Al surface are compared. It is found that zincating replacement on the Al-Si-Cu surface is much more rapid than on the Al surface and the dissolution rate of Al-Si-Cu is also faster than that of Al. Finally, the quality of the low-cost solder bumping process is evaluated by shear tests and reliability tests.

Investigation of electroplating Ni UBM for Pb-free solders

The use of Pb in electronics will be prohibited due to its toxicity so it is important to find a reliable under bump metallurgy (UBM) for lead-free solder applications. Electroplating Ni (E-NI) as a UBM has potential, and therefore the more detailed investigations of E-NI UBM for eutectic SnAgCu and SnPb solders are reported in this paper. In order to compare the results with E-Ni UBM, electroplating Cu (E-Cu) and electroless Ni(P) plating [Eless-Nip)] UBM for eutectic SnAgCu or SnPb solders were also studied. The thin film stress was measured using a laser scanning profiler and the Stoney equation. The interfacial reactions were analyzed by grazing incidence X-ray diffractometly (GIXRD), scanning electron microscopy (SEM) and transmission electron microscopy (TEM) in conjunction with energy dispersive analysis of X-ray (EDAX). The E-NI thin film had lower stress compared to E-Cu and Eless-Ni(P) thin films. Not only the dominant phase (NiCu),S& was found at the ENi/SnAgCu interface, but also many small precipitated particles identified to be Ag3Sn phase were found on the surface of (NiCu),Sn, grains. The growth rates of IMC between E-Ni/SnAgCu and E-CdSnAgCu samples were found to be similar. However, the large difference of IMC growth rates between E-NilSnPb and E-CdSnPb samples was also noticed. Through the shear tests, the fracture mode was found to change from solder hall fracture mode to the mixed mode containing solder ball fracture and delamination from the IMC/solder interface for the samples after I O and 20 times of solder reflow. However, the average shear strength was not found to decrease obviously.

The evaluation of flip chip bumping on Cu/low-/spl kappa/ wafer

Recently, flip chip package has obtained more and more attentions due to its benefits of high I/O, low inductance and better thermal dissipation. Therefore flip chip package is getting to be used in some high performance and high speed devices such as microprocessor, chipset, and etc. Today semiconductor fabrication is going to the generation of Cu interconnection and low-/spl kappa/ dielectric in order to meet the Moores Law. The mechanical (such as hardness, toughness, tensile strength, film stress, CTE and etc.), physical (such as adhesion to metal, thermal stability) and chemical properties of low-/spl kappa/ material, especially the so-called spin-on dielectrics, are very different to those of silicon oxide and nitride because they are composed of soft organic polymer. In flip chip bumping on low-/spl kappa/ dielectric material, the major issue we have to consider is the stress resulted from UBM and solder process will induce the crack or delamination between copper and low-/spl kappa/ dielectric layer. So in this paper we use two kinds of low-/spl kappa/ material, PI 2610 (/spl kappa/=2.9) and SiLK (/spl kappa/=2.6), and two types of UBM material, electroplated copper and electroless nickel, to investigate the influence of UBM material on the mechanical performance of flip chip bumping (e.g. shear force). Besides UBM materials, we would evaluate the effect of UBM size and reflow on bumping quality.

Design optimization and analysis of a novel nanocomposite-film typed flip chip technology

This paper aims at developing an effective scheme for design optimization of a novel nanocomposite-typed flip chip (FC) technology, constructed by integrating an Ag-nanowire/polymer nanocomposite film together with a nonconductive paste (NCP) technology. The objective of the optimization problem is to achieve the optimal process-induced thermal-mechanical behaviors of the novel FC technology during the NCP bonding process through the selection of material properties, process parameters and geometry data. The process-induced thermal-mechanical behaviors are evaluated using a process-dependent simulation methodology that integrates both transient thermal and nonlinear contact FE analyses and a “death-birth” meshing scheme. The validity of the process-dependent FE simulation methodology is also confirmed through experiment. To demonstrate the effectiveness of the present design optimization approach, several design problems associated with the FC technology are performed.

Mechanical Process Simulation of a Novel Metal-Nanowire-Film-based Flip Chip Technology

The study aims at developing a next-generation flip chip (FC) packaging technology that employs a novel anisotropic conductive adhesive (ACF) made of unidirectional Co-nanowire-reinforced polymer nanocomposite, and moreover, exploring the associated process-induced, thermal-mechanical behaviors during bonding process. For carrying out the process simulation, a process-dependent finite element modeling (FEM) methodology is proposed. The investigation starts from the theoretical and experimental assessments of the elastic properties the nanoscale Co metal using molecular dynamics (MD) simulations and nanoindentation testing, respectively, followed by the determination of the thermal-mechanical material properties of the nanocomposite, using the proposed FEM-based effective modeling approach. The predicted results are compared with those obtained from the widely-used rule-of-mixture (ROM) technique and existing analytical models, and also, with those from experimental measurements. At last, factors that most influence on the thermal-mechanical behaviors of the novel technology are also investigated through parametric FE analysis and Taguchi method.