Russell Schreiber

Carrizo: A High Performance, Energy Efficient 28 nm APU

AMDs 6th generation “Carrizo” APU, targeted at 12-35 W mobile computing form factors, contains 3.1 billion transistors, occupies 250.04 mm 2 and is implemented in a 28 nm HKMG planar dual-oxide FET technology with 12 metal layers. The design achieves a 29% improvement in transistor density compared to the 5th generation “Kaveri” APU, also a 28 nm design, and implements several power management features resulting in area and power improvements similar to a technology shrink. Increased power density makes meeting the thermal limits required for reliability and power distribution to the APUs processors substantial design challenges. Pre-silicon thermal analysis is used to understand and take advantage of thermal gradients. Adaptive voltage-frequency scaling in the processor core as well as wordline and bitline assist techniques in the L2 cache enable lower minimum voltage requirements.

4.8 A 28nm x86 APU optimized for power and area efficiency

Carrizo (CZ, Fig. 4.8.7) is AMDs next-generation mobile performance accelerated processing unit (APU), which includes four Excavator (XV) processor cores and eight Radeon™ graphics core next (GCN) cores, implemented in a 28nm HKMG planar dual-oxide FET technology featuring 3 Vts of thin-oxide devices and 12 layers of Cu-based metallization. This 28nm technology is a density-focused version of the 28nm technology used by Steamroller (SR) [1] featuring eight 1× metals for dense routing, one 2× and one 4× for low-RC routing and two 16x metals for power distribution.

An 8MB level-3 cache in 32nm SOI with column-select aliasing

High-performance multi-core processors require efficient multi-level cache hierarchies to meet high-bandwidth data requirements. Because level-3 (L3) cache is typically the largest cache on the die, the drive to lower cost places pressure on density, yields, and test time. Performance-per-watt goals and total power constraints also compel a variety of circuit techniques to reduce power. The next-generation server processor codenamed “Orochi”, implemented on a 32nm high-k metal-gate SOI process with 11 metal layers, consists of four 2-core modules using AMDs next-generation architecture, code named “Bulldozer”, with 2MB of dedicated L2 cache per module and an 8MB shared L3 cache [1].