John J. Wuu

32nm high-density high-speed T-RAM embedded memory technology

Thyristor Random Access Memory (T-RAM) is an ideal candidate for application as an embedded memory due to its substantially better density vs. performance tradeoff and logic process compatibility [1–3]. T-RAM memory embedded in a 32nm logic process with read and write times of 1ns and a bit fail rate less than 0.5ppm is reported for the first time. T-RAM memory cell median read current of 250µA/cell at 1.2V with an Ion/Ioff current ratio of more than 108 is demonstrated at 105°C. Robust margins to dynamic disturb due to the access (read/write) of neighboring bits in the memory array have also been verified.

A 2ns-read-latency 4Mb embedded floating-body memory macro in 45nm SOI technology

To meet advancing market demands, microprocessor embedded memory applications require denser and faster memory arrays with each process generation. Recent work presented an 18.5ns 128Mb DRAM with a floating body cell for conventional DRAM products [1] and a 4Mb memory macro using a memory cell built with two floating body transistors [2]. This paper presents a floating-body Z-RAM® memory cell [3] to fabricate a high-density low-latency and high-bandwidth 4Mb memory macro building block, targeted at the requirements of microprocessor caches. It uses a single transistor (1T), unlike traditional 1T1C DRAM [4], or six transistor 6T-SRAM memory cells [5].

An 8MB level-3 cache in 32nm SOI with column-select aliasing

High-performance multi-core processors require efficient multi-level cache hierarchies to meet high-bandwidth data requirements. Because level-3 (L3) cache is typically the largest cache on the die, the drive to lower cost places pressure on density, yields, and test time. Performance-per-watt goals and total power constraints also compel a variety of circuit techniques to reduce power. The next-generation server processor codenamed “Orochi”, implemented on a 32nm high-k metal-gate SOI process with 11 metal layers, consists of four 2-core modules using AMDs next-generation architecture, code named “Bulldozer”, with 2MB of dedicated L2 cache per module and an 8MB shared L3 cache [1].