Ryan Fung

Simultaneous short-path and long-path timing optimization for FPGAs

This work presents the routing cost valleys (RCV) algorithm - the first published algorithm that simultaneously optimizes all short- and long-path timing constraints in a field-programmable gate array (FPGA). RCV is comprised of a new slack allocation algorithm that produces both minimum and maximum delay budgets for each circuit connection, and a new router that strives to meet and, if possible, surpass these connection delay constraints. RCV achieves excellent results. On a set of 100 large circuits, RCV improves both long-path and short-path timing slack significantly vs. an earlier computer-aided design (CAD) system that focuses solely on long-path timing. Even with no short-path timing constraints, RCV improves the clock speed of circuits by 3.9% on average. Finally, RCV is able to meet timing on all 72 peripheral component interconnect (PCI) cores tested, while an earlier algorithm fails to achieve timing on all 72 cores.

A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs

Metastability is a phenomenon that can cause system failures in digital circuits. It may occur whenever signals are being transmitted across asynchronous or unrelated clock domains. The impact of metastability is increasing as process geometries shrink and supply voltages drop faster than transistor Vts. FPGA technologies are significantly affected since leading edge FPGAs are amongst the first devices to adopt the most recent process nodes. In this paper, we present a comprehensive suite of techniques for modeling, characterizing and optimizing metastability effects in FPGAs. We first discuss a theoretical model of metastability, and verify the predictions using both circuit level simulations and board measurements. Next we show how designers have traditionally dealt with metastability problems and contrast that with the automatic CAD algorithms described in this paper that both analyze and optimize metastability-related issues. Through our detailed experimental results, we show that we can improve the metastability characteristics of a large suite of industrial benchmarks by an average of 268,000 times with our optimization techniques.

Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations

This paper presents the first published algorithm to simultaneously optimize both short- and long-path timing in a field-programmable gate array (FPGA): the routing cost valleys (RCV) algorithm. RCV consists of the following two components: a new slack-allocation algorithm that determines both a minimum and a maximum delay budget for each circuit connection and a new router that strives to meet and, if possible, surpass these connection-delay constraints. RCV improves both long- and short-path timing slacks significantly versus an earlier computer-aided design system, showing the importance of an integrated approach that simultaneously optimizes considering both types of timing constraints. It is able to meet long- and short-path timing constraints on all 157 peripheral component interconnect cores tested, while an earlier algorithm failed to achieve timing on 75% of the cores. Even in cases where there are no short-path timing constraints, RCV outperforms a state-of-the-art FPGA router and improves the maximum clock speed of circuits by an average of 3.2% (and up to 24.7%).