Andy L. Lee

The Stratix II logic and routing architecture

This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be partitioned into two smaller LUTs to efficiently implement circuits containing a range of LUT sizes that arises in conventional synthesis flows. This provides a performance increase of 15% in the Stratix II architecture while reducing area by 2%. The ALM also includes a more powerful arithmetic structure that can perform two bits of arithmetic per ALM, and perform a sum of up to three inputs. The routing fabric adds a new set of fast inputs to the routing multiplexers for another 3% improvement in performance, while other improvements in routing efficiency cause another 6% reduction in area. These changes in combination with other circuit and architecture changes in Stratix II contribute 27% of an overall 51% performance improvement (including architecture and process improvement). The architecture changes reduce area by 10% in the same process, and by 50% after including process migration.

The stratixπ routing and logic architecture

This paper describes the Altera Stratix logic and routing architecture. The primary goals of the architecture were to achieve high performance and logic density. We give an overview of the entire device, and then focus on the logic and routing architecture. The Stratix logic architecture is based on a cluster of ten 4-input LUTs and its routing consists of staggered routing lines. We describe the development of the routing architecture, including its directional bias, its direct-drive routing which reduces both area and delay. The logic array block and logic cell design is also described, and new routing structures with in the logic array block, and logic element features are described.

Improving FPGA Performance and Area Using an Adaptive Logic Module

This paper proposes a new adaptable FPGA logic element based on fracturable 6-LUTs, which fundamentally alters the longstanding belief that a 4-LUT is the most efficient area/delay tradeoff. We will describe theory and benchmarking results showing a 15% performance increase with 12% area de- crease vs. a standard BLE4. The ALM structure is one of a number of archi- tectural improvements giving Alteras 90nm Stratix II architecture a 50% per- formance advantage over its 130nm Stratix predecessor.

A next generation architecture optimized for high density system level integration

Altera has developed a next generation architecture called APEX/sup TM/ to improve overall logic efficiency, performance and provide a framework to add a much broader range of features which enables complete system level integration of a users system. This new architecture will support a family of devices exceeding 2 million gates in density. Density and speed improvements are achieved through an enhanced hierarchical routing structure.