Ryan Robucci

Compressive sensing on a CMOS separable transform image sensor

This paper demonstrates a computational image sensor capable of implementing compressive sensing operations. Instead of sensing raw pixel data, this image sensor projects the image onto a separable 2-D basis set and measures the corresponding expansion coefficients. The inner products are computed in the analog domain using a computational focal plane and an analog vector-matrix multiplier (VMM). This is more than mere postprocessing, as the processing circuity is integrated as part of the sensing circuity itself. We implement compressive imaging on the sensor by using pseudorandom vectors called noiselets for the measurement basis. This choice allows us to reconstruct the image from only a small percentage of the transform coefficients. This effectively compresses the image without any digital computation and reduces the throughput of the analog-to-digital converter (ADC). The reduction in throughput has the potential to reduce power consumption and increase the frame rate. The general architecture and a detailed circuit implementation of the image sensor are discussed. We also present experimental results that demonstrate the advantages of using the sensor for compressive imaging rather than more traditional coded imaging strategies.

Compressive Sensing on a CMOS Separable-Transform Image Sensor

This paper demonstrates a computational image sensor capable of implementing compressive sensing operations. Instead of sensing raw pixel data, this image sensor projects the image onto a separable 2-D basis set and measures the corresponding expansion coefficients. The inner products are computed in the analog domain using a computational focal plane and an analog vector-matrix multiplier (VMM). This is more than mere postprocessing, as the processing circuity is integrated as part of the sensing circuity itself. We implement compressive imaging on the sensor by using pseudorandom vectors called noiselets for the measurement basis. This choice allows us to reconstruct the image from only a small percentage of the transform coefficients. This effectively compresses the image without any digital computation and reduces the throughput of the analog-to-digital converter (ADC). The reduction in throughput has the potential to reduce power consumption and increase the frame rate. The general architecture and a detailed circuit implementation of the image sensor are discussed. We also present experimental results that demonstrate the advantages of using the sensor for compressive imaging rather than more traditional coded imaging strategies.

MATIA: a programmable 80 /spl mu/W/frame CMOS block matrix transform imager architecture

In this paper, we introduce our CMOS block MAtrix Transform Imager Architecture (MATIA). This imager is capable of performing programmable matrix operations on an image. The imager architecture is both modular and programmable. The pixel used in this architecture performs matrix multiplication while maintaining a high fill factor (46%), comparable to active pixel sensors. Floating gates are used to store the arbitrary matrix coefficients on-chip. The chip operates in the subthreshold domain and thus has low power consumption (80 /spl mu/W/frame). We present data for different convolutions and block transforms that were implemented using this architecture, and also present data from baseline JPEG and motion JPEG systems which we have implemented using MATIA.

A Low-Power, Compact, Adaptive Logarithmic Transimpedance Amplifier Operating Over Seven Decades of Current

This paper presents a detailed insight into the design space of wide-range transimpedance amplifiers enabling the design of micro-power, adaptive circuits for integrated current sensing applications. The analysis proves that the power dissipation of the nonadaptive structures varies linearly with dynamic range and quadratically with bandwidth. We present two adaptation techniques, modifying the bias current or output resistance, both of which alleviate this strong dependence on dynamic range. It is shown that adapting the bias current is most suitable for our application which requires a modest bandwidth but very wide dynamic range. Measurements demonstrate operation with currents ranging seven orders of magnitude from 200 fA to 2 muA with an average error of 0.8% and maximum error of 3.4%. The power consumption averaged over this entire range of currents is 3.45 muW . Either signal-to-noise ratio (SNR) or bandwidth can be made to tradeoff with the input current magnitude depending on the application. If the bandwidth is limited to 5 kHz, it achieves an average SNR of 65 dB.

Inviz: Low-power personalized gesture recognition using wearable textile capacitive sensor arrays

Home automation and environmental control is a key ingredient of smart homes. While systems for home automation and control exist, there are few systems that interact with individuals suffering from paralysis, paresis, weakness and limited range of motion that are common sequels resulting from severe injuries such as stroke, brain injury, spinal cord injury and many chronic (guillian barre syndrome) and degenerative (amyotrophic lateral sclerosis) conditions. To address this problem, we present the design, implementation, and evaluation of Inviz, a low-cost gesture recognition system for paralysis patients that uses flexible textile-based capacitive sensor arrays for movement detection. The design of Inviz presents two novel research contributions. First, the system uses flexible textile-based capacitive arrays as proximity sensors that are minimally obtrusive and can be built into clothing for gesture and movement detection in patients with limited body motion. The proximity sensing obviates the need for touch-based gesture recognition that can cause skin abrasion in paralysis patients, and the array of capacitive sensors help provide better spatial resolution and noise cancellation. Second, Inviz uses a low-power hierarchical signal processing algorithm that breaks down computation into multiple low and high power tiers. The tiered approach provides maximal vigilance at minimal energy consumption. We have designed and implemented a fully functional prototype of Inviz and we evaluate it in the context of an end-to-end home automation system and show that it achieves high accuracy while maintaining low latency and low energy consumption.

A 80 /spl mu/W/frame 104/spl times/128 CMOS imager front end for JPEG compression

We present a programmable 80 /spl mu/W/frame (3.3 V supply) single-chip architecture that combines a CMOS imager and an analog image processor capable of computing separable block matrix transforms (DCT, Haar, etc). Floating-gate technology is used for on-chip kernel storage and also for performing low-power current-mode matrix multiplications. We demonstrate this IC as a front-end for JPEG compression and compare the performance of this imager to fully digital approaches.

A Low-Power, Compact, Adaptive Logarithmic Transimpedance Amplifier Operating over Seven Decades of Current

This paper presents a detailed insight into the design space of wide-range transimpedance amplifiers enabling the design of micro-power, adaptive circuits for integrated current sensing applications. The analysis proves that the power dissipation of the nonadaptive structures varies linearly with dynamic range and quadratically with bandwidth. We present two adaptation techniques, modifying the bias current or output resistance, both of which alleviate this strong dependence on dynamic range. It is shown that adapting the bias current is most suitable for our application which requires a modest bandwidth but very wide dynamic range. Measurements demonstrate operation with currents ranging seven orders of magnitude from 200 fA to 2 muA with an average error of 0.8% and maximum error of 3.4%. The power consumption averaged over this entire range of currents is 3.45 muW . Either signal-to-noise ratio (SNR) or bandwidth can be made to tradeoff with the input current magnitude depending on the application. If the bandwidth is limited to 5 kHz, it achieves an average SNR of 65 dB.

Adaptive and Personalized Gesture Recognition Using Textile Capacitive Sensor Arrays

Upper extremity mobility impairment is a common sequel of Spinal Cord Injury (SCI), brain injury, strokes, and degenerative diseases such as Guillain-Barre and ALS. Existing assistive technology solutions that provide access as user input devices are intrusive and expensive, and require physical contact that can have deleterious effects such as skin friction injury for paralyzed users who have reduced skin sensitivity. To address this problem, in this paper, we present the design, implementation, and evaluation of a non-contact proximity gesture recognition system using fabric capacitive sensor arrays. The fabric sensors are lightweight, flexible, and can be easily integrated into items of quotidian use such as clothing, bed sheets, and pillow covers. Our gesture recognition algorithm builds on two known classification techniques, Hidden Markov Model and Dynamic Time Warping to convert raw capacitance values to alphanumeric gestures. Our system is personalized to the user, allowing personalized selection of gesture sets and definition of gesture patterns in accordance with their capabilities. Our system adapts to changes in sensor configuration and orientation with minimal user training and intervention. We have evaluated our system in the context of a gesture-driven home automation system on six subjects that includes an individual who has a C6 Spinal Cord injury. We show that our system can recognize gestures of varying complexity with an average accuracy of 99 percent with minimal training.

Estimating Power Supply Noise and its impact on path delay

Power Supply Noise has a significant impact on path delay and therefore its estimation is critical in delay testing. In deep sub-micron technologies, voltages are scaled and the number of switching gates has increased which make chips susceptible to power supply noise. Running full-chip simulations on large designs to predict the noise is time consuming and expensive. Therefore, most existing techniques are based on statistical approaches. In this paper, we propose a current-based dynamic method to estimate power supply noise and use the framework to predict the increase in path delay caused by the variations in power supply voltage without carrying out a full-chip simulation. A convolution-based technique is used to compute the path delays where standalone paths are extracted and simulated. Experimental results reported for estimating noise using the ISCAS-85 benchmark circuit are within 10% of full-chip results. The delay predictions carried out on two other experimental designs using our technique closely match full-chip results with a maximum error of 2%.

Tongue-n-cheek: non-contact tongue gesture recognition

Tongue gestures are a key modality for augmentative and alternative communication in patients suffering from speech impairments and full-body paralysis. Systems for recognizing tongue gestures, however, are highly intrusive. They either rely on magnetic sensors built into dentures or artificial teeth deployed inside a patients mouth or require contact with the skin using electromyography (EMG) sensors. Deploying sensors inside a patients mouth can be uncomfortable for long-term use and contact-based sensors like EMG electrodes can cause skin abrasion. To address this problem, we present a novel contact-less sensor, called Tongue-n-Cheek, that captures tongue gestures using an array of micro-radars. The array of micro-radars act as proximity sensors and capture muscle movements when the patient performs the tongue gesture. Tongue-n-Cheek converts these movements into gestures using a novel signal processing algorithm. We demonstrate the efficacy of Tongue-n-Cheek and show that our system can reliably infer gestures with 95% accuracy and low latency.