Jordan D. Gray

Compressive sensing on a CMOS separable transform image sensor

This paper demonstrates a computational image sensor capable of implementing compressive sensing operations. Instead of sensing raw pixel data, this image sensor projects the image onto a separable 2-D basis set and measures the corresponding expansion coefficients. The inner products are computed in the analog domain using a computational focal plane and an analog vector-matrix multiplier (VMM). This is more than mere postprocessing, as the processing circuity is integrated as part of the sensing circuity itself. We implement compressive imaging on the sensor by using pseudorandom vectors called noiselets for the measurement basis. This choice allows us to reconstruct the image from only a small percentage of the transform coefficients. This effectively compresses the image without any digital computation and reduces the throughput of the analog-to-digital converter (ADC). The reduction in throughput has the potential to reduce power consumption and increase the frame rate. The general architecture and a detailed circuit implementation of the image sensor are discussed. We also present experimental results that demonstrate the advantages of using the sensor for compressive imaging rather than more traditional coded imaging strategies.

Large-scale field-programmable analog arrays for analog signal processing

Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality and flexibility. For FPAAs to enter the realm of large-scale reconfigurable devices such as modern field-programmable gate arrays (FPGAs), new technologies must be explored to provide area-efficient accurately programmable analog circuitry that can be easily integrated into a larger digital/mixed-signal system. Recent advances in the area of floating-gate transistors have led to a core technology that exhibits many of these qualities, and current research promises a digitally controllable analog technology that can be directly mated to commercial FPGAs. By leveraging these advances, a new generation of FPAAs is introduced in this paper that will dramatically advance the current state of the art in terms of size, functionality, and flexibility. FPAAs have been fabricated using floating-gate transistors as the sole programmable element, and the results of characterization and system-level experiments on the most recent FPAA are shown.

Compressive Sensing on a CMOS Separable-Transform Image Sensor

This paper demonstrates a computational image sensor capable of implementing compressive sensing operations. Instead of sensing raw pixel data, this image sensor projects the image onto a separable 2-D basis set and measures the corresponding expansion coefficients. The inner products are computed in the analog domain using a computational focal plane and an analog vector-matrix multiplier (VMM). This is more than mere postprocessing, as the processing circuity is integrated as part of the sensing circuity itself. We implement compressive imaging on the sensor by using pseudorandom vectors called noiselets for the measurement basis. This choice allows us to reconstruct the image from only a small percentage of the transform coefficients. This effectively compresses the image without any digital computation and reduces the throughput of the analog-to-digital converter (ADC). The reduction in throughput has the potential to reduce power consumption and increase the frame rate. The general architecture and a detailed circuit implementation of the image sensor are discussed. We also present experimental results that demonstrate the advantages of using the sensor for compressive imaging rather than more traditional coded imaging strategies.

A Precision CMOS Amplifier Using Floating-Gate Transistors for Offset Cancellation

A long-term offset cancellation scheme that enables continuous-time amplifier operation is described. Offset cancellation is achieved by programming floating-gate transistors that form an integral part of the amplifiers architecture. The offset voltage of a single-stage folded cascode amplifier has been programmed to a minimum of plusmn25 muV in a 0.5 mum digital CMOS process. The long-term offset voltage drift has been calculated to be less than 0.5 muV over a period of 10 years at 55degC from a thermionic emission model for floating-gate charge loss. The offset voltage varies by a maximum of 130 muV over a temperature range of 170degC, thereby making this a viable approach to offset cancellation

Characteristics and programming of floating-gate pFET switches in an FPAA crossbar network

A floating-gate pFET is a desirable switch element for use in a crossbar switch due to it having a resistance on the order of a transmission gate, the capacitance of a single pass-FET, and requires no digital memory to store the state of the switch. As a result, a floating-gate pFET crossbar network can achieve a higher bandwidth than a transmission gate based network. In addition, the resulting floating-gate implementation has a smaller silicon footprint than an array of transmission gates with the necessary support structures. Finally, the resistance of the floating-gate switch is achieved by modulating the input gate voltage during channel hot-electron injection.

A precision CMOS amplifier using floating-gates for offset cancellation

A long-term offset cancellation scheme that enables continuous-time amplifier operation is described. Offset cancellation is achieved by programming floating-gate transistors that form an integral part of the amplifiers architecture. The offset voltage of a single-stage folded cascode amplifier is reduced to plusmn25 muW in a 0.5mum digital CMOS process. The offset voltage drift is 0.5 muV over a period of 10 years at 25degC and varies by a maximum of 130muV over a temperature range of 170degC

A field-programmable analog array using translinear elements

A field programmable analog array that uses translinear elements for computation is introduced. The system uses floating-gate transistors to implement switch networks and MITEs to create reconfigurable translinear networks. The system architecture includes 3 MITE CABs, 1 specialized CAB for implementing four quadrant and dynamic functions, and a global switch matrix used to connect them. A squaring circuit, a square root circuit, a 2nd-order translinear loop, a vector magnitude circuit, and a 1st-order log-domain filter are programmed onto the device and results are presented in order to demonstrate the reconfigurability of the system.

A 256×256 separable transform CMOS imager

This paper discusses a 256times256 computational imager capable of performing separable transforms. Unlike traditional imagers, this imager performs computation on-chip and in- pixel. The primary computation performed is a separable matrix transformation. Several developments were made since a previous matrix transform imager to expand functionality and resolution. New circuit design emphasized dynamic range, accuracy, and speed. This architecture includes a novel overlapping block scheme allowing 8times8 general separable 2-D convolutions as well as 16times16 block transforms.

The design and simulation model of an analog floating-gate computational element for use in large-scale analog reconfigurable systems

We present the methodology for implementing a computational memory element using a floating-gate pFET model suitable for the design and simulation of analog systems. A first-order physically inspired model of pFET hot-election injection is implemented in Verilog-A, fit to experimental data, and then applied to a proposed floating-gate circuit. The model parameters are fit directly to the drain current data from a measured floating-gate pFET, eliminating the need for estimating or measuring gate injection current. The model is used to examine the programming transient response of a proposed analog computational vector-matrix multiplier cell. The circuit eliminates power-supply ramping by using a negative voltage, avoids complex characterization by linearized the injection current, and reduces off-chip interaction with on-chip feedback. We discuss how our model and approach represent a pathway for accessible floating-gate design, simulation, and implementation.

Parasitic charge movement in floating-gate array programming

Floating-gate charge storage is a key analog VLSI system technique. As the number of floating-gate elements in such VLSI systems increase, the relative area of the analog memory cell and its supporting circuitry become more critical. The compact floating-gate selection and isolation circuitry used in large-scale analog arrays is often based on a flawed assumption: that subthreshold conduction is the dominant source of parasitic charge movement associated with array isolation. The parasitic charge movement is primarily a combination of subthreshold conduction, PN-junction reverse bias current enhanced by gate-overlap, and Fowler-Nordheim tunneling. As a result, array isolation designed specifically to minimize subthreshold conduction can actually enhance the overall parasitic charge movement, leading to programming accuracy degradation. A procedure and experimental data demonstrating parasitic charge movement is shown for a device in an array fabricated on a 0.35 um process. Software and hardware hardware techniques for addressing and eliminating parasitic charge movement are discussed.