Ryoichi Kajiwara

Au Bump Interconnection with Ultrasonic Flip-Chip Bonding in 20 µm Pitch

Superfine flip-chip bonding technologies in 20 µm pitch microbumps on copper through-hole electrodes are substantial technologies for three-dimensional (3D) chip stacking LSI. As the advanced interconnection technology to connect the through-hole electrodes at low temperature and low bonding force, the ultrasonic flip-chip bonding (UFB) was verified by the total evaluation and the atomic-level analysis of the bonding interface on the chip-on-chip (COC) structure utilizing electroplated Au microbumps in 20 µm pitch. First, the lower limit bonding conditions were confirmed to be a bonding force of 20 N and an amplitude of 3 µm; the bonding accuracy achieved was within ±2 µm, the electrical interface resistance was stable about 0.57 Ω, and no damage around the interconnection structure was observed. Secondly, the mechanism of solid phase bonding interface formation at the atomic level without solid phase diffusion was confirmed as the Au-Au solid phase UFB bonding mechanism, and the orientation geometry of such bonding was apparently different from that of thermo compression bonding, which showed solid phase diffusion across the boundary. The achievement of this research will enable the realization of the 3D chip stacking LSI in the near future, which is characterized by scalabilities and high-performance. The subjects are the elucidation of the real oscillation contributes to bonding to optimize the process conditions and the establishment of the micro joint reliabilities utilizing UFB process.

Au Bump Interconnection in 20 µm Pitch on 3D Chip Stacking Technology

The three-dimensional (3D) chip stacking LSI technology under development in Association of Super-Advanced Electronic Technologies (ASET) is a new packaging technology for realizing high-density and high-speed transmission, and superfine flip-chip bonding technologies utilizing 20-µm-pitch micro bumps on Cu through hole electrodes are substantial technologies. There are two key technical issues involved in realizing the 3D chip stacking LSI. One is the provision of the sufficient interconnections, which have low resistivity and which are absolutely connected. Another is the reduction of the thermal stress of the micro bumps by providing encapsulated resin between devices. Regarding the metallurgically stable and low electrical resistance interconnections, electroplated Au bump bonding in 20-µm-pitch by thermo compression bonding process was evaluated on the chip-on-chip(COC) structure. First, the softening of the Au bump by annealing was confirmed, and was expected to decrease the bonding stress of the under bump structure. Second, the lower limit bonding conditions were confirmed to be a bonding force of 24.5 N at 350°C, and the electrical resistance was confirmed to be stable at about 0.55 Ω. The mechanism of Au–Au thermo compression bonding with the solid phase diffusion across the boundary was confirmed. Finally, the life of the 20-µm-pitch interconnection with the underfillresin containing the hyperfine filler particles under temperature cycling tests (TCT) was more than 1000 cycles, which is an acceptable level for a semiconductor package. This research will enable the realization of 3D chip stacking LSI in the near future which features scalability and high performance. The subjects are the verification of the appropriate bump dimensions in order to further improve the reliability and the realization of the interconnection reliability on 3D chip stacking LSI.

New Method for Estimating Impact Strength of Solder-Ball-Bonded Interfaces in Semiconductor Packages

A method for estimating the impact strength of a solder ball junction in encapsulated semiconductor packages was developed. This method reveals the impact force in a solder ball unit and the time required for a solder ball to break. The bombardment absorbed energy required for the ball to break is evaluated as impact strength. This method can be used to quantitatively evaluate the impact strength of solder ball junctions, which is difficult to do using conventional shear and tensile strength estimation methods.