Ryotaro Kobayashi

An on-chip multiprocessor architecture with a non-blocking synchronization mechanism

The growth of perception that the superscalar approach is reaching its limits drives studies of on-chip multiprocessor (MP) architectures as the alternative. This paper proposes a new MP architecture, called SKY: which efficiently exploits thread-level parallelism using register-value communication and synchronization. The most distinctive feature of SKY from previously proposed MP architectures is its synchronization mechanism with non-blocking capability. It allows any subsequent instruction that is independent of instructions waiting for registers to be executed, enabling continuous out-of-order execution independently of inter-thread communication and synchronization. Our evaluation results in SPECint95 benchmark programs show that SKY with two processors achieves a speedup of up to 40% or an average of 12% over a much more complex single wide-issue superscalar processor with the nearly same amount of hardware.

Detection of the DNS Water Torture Attack by Analyzing Features of the Subdomain Name

The Domain Name System (DNS), whose major function is to manage associations between domain names and IP addresses, plays a major role in managing the Internet. Thus, a DNS impairment would significantly impact society. A major cause of DNS impairment is Distributed Denial of Service (DDoS) attack on authoritative DNS servers. Our study focuses on the recently emerging DDoS attack known as the DNS Water Torture Attack. This attack causes open resolvers, which are improperly configured cache DNS servers that accept requests from both LAN and WAN, to send many queries to resolve domains managed by target servers. Domain names for resolving sent in this attack include varying random subdomains. Cache servers certainly will not have cached data for these queries, and so a huge volume of queries converges to the target authoritative servers via cache servers. In this paper, we propose a detection method for this attack using the Naive Bayes Classifier. Experimental results show that our method is capable of detecting this attack with a 95.59% detection rate. Moreover, the results of performance simulation show that our method is fast enough to process more than 2.3 Gbps of traffic on the fly.

A novel low-power processor with variable pipeline control

One of the most attractive issues for microprocessors is low power design. So far there are many techniques has been used, but most of them are applied at the device level or at the circuit level. In this paper, we propose a novel technique applied at the architecture level. It reduces power consumption by controlling pipeline length. To attain arbitrary performance, we use proportional-integral control to adjust pipeline length and the control mechanism is implemented on-chip. The experimental results show that the mechanism can reduce power consumption by up to 14.1% and energy consumption by up to 23.0% compared with Dynamic Voltage and Frequency Scaling.

Energy Reduction of BTB by Focusing on Number of Branches per Cache Line

The latest processors exploit Instruction Level Parallelism to improve performance, but this strategy is limited by control dependency. To alleviate this problem, the most recent processors utilize branch prediction. A typical branch predictor applies prediction to all instructions; however, this means that the branch predictor requires a high energy input, especially to the BTB (branch target buffer). In this paper, we propose a method that reduces the number of BTB accesses and abolishes the BTB tag by associating the instruction cache line and BTB entry. This proposal allocates a fixed number of BTB entries to a cache line and allocates an index to the corresponding instruction in the cache line as a substitute for the BTB tag. Due to the small fixed numbers of BTB entries compared to the fetch amount and reduction of the BTB tag, our proposal can reduce BTB access energy requirements. Our proposal is anticipated to cut energy consumption, but it cannot apply a branch target prediction to the entire set of instructions if there are too many branch instructions per cache line. We therefore evaluated its effects on processor performance and energy consumption. The evaluation results show that the proposal reduces BTB access energy requirements to 47.5% without any performance loss.

Reduction of cache energy by switching between L1 high speed and low speed cache under application of DVFS

Recent CPU widely utilizes cache memory or cache to decrease access speed gap between the CPU and the main memory. However, the cache occupies a large part of the processors energy consumption. Furthermore, due to the characteristics of SRAMs, it is hard to reduce the supply voltage of the cache compared to that of the CPU core. Thus, dynamic voltage and frequency scaling (DVFS) which is widely used to reduce the processors energy consumption does not reduce cache energy significantly. To confront this problem, we investigated a method which applies different power and speed design caches and switching them in proportion to the DVFS activity. Our proposal modifies the L1 cache hierarchy to L1 low-speed cache and L1 high-speed cache and selects them or access in sequential in proportion to DVFS activity to reduce cache energy demand. We confirmed that the proposal has a potential for further reduction of cache energy consumption with both cache design simulation and processor architecture level simulation.

Instruction rearrangement and path limitation for ALU cascading

Nowadays, many-core processors utilize 2-way in-order execution cores due to good area/energy efficiency. Those cores are diverted from high-performance embedded processor so that it is convenient from the core development cost viewpoint. We can easily create 3-way in-order execution unit as a simple expansion of 2-way in-order execution. However, it makes few IPC improvement due to data dependency of instructions. Applying ALU cascading to 3-way in-order execution is a effective solution to alleviate this problem. In this study, we proposed a mechanism which limits cascading data path in ALU stage. Due lo lightweight data path, we improved both power consumption and delay in ALU stage of the processor. This study showed that the proposed mechanism can reduce the circuit area by 5.5% and the power consumption by 9.2% on average.

Power consumption reduction scheme focusing on the Depth of Speculative Execution

A mechanism is proposed that reduces power consumption, and which focuses on the speculative execution depth (SED). SED is the number of branch instructions whose results are not yet known in the processor. The mechanism controls the SED depending on the current workload. The evaluation results show that the proposed scheme can reduce power consumption by 10.8-41.0% when the target throughput ranges from 60-90%, and suppress the average error margin with the target throughput to 1.0% or less.