Ryouji Kosugi

Fixed nitrogen atoms in the SiO2/SiC interface region and their direct relationship to interface trap density

Nitrogen atoms fixed in the SiO2/SiC interface region were studied by x-ray photoelectron spectroscopy (XPS) and capacitance-voltage (C-V) measurements. A thin oxide film (<5 A) formed during annealing in an NO atmosphere on a (0001) 4H-SiC surface, incorporating nitrogen atoms into the interface region. Even after complete removal of the oxide layer by etching in hydrofluoric acid, XPS spectra clearly showed a strong N 1 s peak, revealing the presence of fixed nitrogen atoms with an areal density of 1014 cm−2 in the interface region. To evaluate their influence on interface traps, metal-oxide-semiconductor capacitors were formed by deposition of a gate oxide layer. The fixed nitrogen atoms decrease the interface trap density after post-annealing at high temperature.

Behavior of nitrogen atoms in SiC-SiO2 interfaces studied by electrically detected magnetic resonance

The microscopic behavior of nitrogen atoms in the SiO2-SiC interface regions of n-channel lateral 4 H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs) was studied using low-temperature electrically detected magnetic resonance spectroscopy and other techniques. The results show that nitrogen atoms eliminated shallow interface states observable at 20 K and further diffused into the channel region of the MOSFETs as shallow donors. These two behaviors enable nitrogen atoms to change the channel conductivity of SiC MOSFETs.

4H-SiC Lateral RESURF MOSFET with a Buried Channel Structure

This paper presents the static characteristics of 4H-SiC lateral R ESU F MOSFET with a buried channel structure. The MOSFET channel mobility was obtained to be as high as 80-90cm/Vs, resulting in the low channel resistance. The RESURF MOSFE T exhibited an on-resistance of 71m Ωcm and a breakdown voltage of 730V. A figure-of-merit ( Vbd / Ron) of this device was calculated to be 7.5MW/cm . Introduction SiC power MOSFET is a promising switching device for high-power el ctronics. Vertical MOSFETs using SiC are extensively investigated as iscrete devices [1-3]. On the other hand, lateral power MOSFET plays an important role in power IC a pplications. SiC RESURF (REduced SURface Field) MOSFETs have been demonstrated by several groups [4-6]. However, high channel resistance because of the poor channel mobility is a se rious problem for the low on-resistance of the SiC power MOSFET. Previously, we have repor ted the high channel mobility in 4H-SiC MOSFETs using the buried channel structure [7, 8]. In this paper, we present the static characteristics of 4H-SiC lateral RESURF MOSFET with a buried channe l structure. Device Design and Fabrication A schematic cross section of a lateral RESURF MOSFET fa bric ted in this study is shown in Fig.1. We adopted the RESURF, a gate field plate and the buried channe l structures in circular-geometric devices. Materials Science Forum Online: 2003-09-15 ISSN: 1662-9752, Vols. 433-436, pp 753-756 doi:10.4028/www.scientific.net/MSF.433-436.753

High Temperature Rapid Thermal Oxidation and Nitridation of 4H-SiC in Diluted N2O and NO Ambient

A high temperature rapid thermal processing (HT-RTP) above 1400oC was investigated for use in the gate oxide formation of 4H-SiC by a cold-wall oxidation furnace. The gate oxide film of ~50nm can be formed for several minutes in the oxidizing atmospheres such as N2O and O2, where the oxidation rates were 8-10nm/min. After the initial oxide formation, the HT-RTPs in various ambient gases were conducted, and the dependences of their MOS interface properties on the gases were evaluated by a capacitance-voltage (CV) measurement. Based on the results, the process sequence of gate oxidation was determined as follows; the initial oxide was formed by the HT-RTO (oxidation) in N2O or in O2 with subsequent post annealing in Ar ambient, and then the HT-RTN (nitridation) in NO was conducted. The total process time becomes 20-50min. The interface trap density (Dit) of fabricated MOS capacitor shows 3-5x1011cm-2eV-1 at Ec-E~0.2eV. The field-effect channel mobility of fabricated 4H-SiC lateral MOSFETs was ~30cm2/Vs.

Filling of Deep Trench by Epitaxial SiC Growth

We performed deep trench filling by using epitaxial SiC growth. It was found that the trench filling condition depend on trench width. A high growth temperature was needed to fill a narrow trench and a low growth temperature was needed to fill a wide trench structure. We optimized the filling condition and successfully filled 7μ m deep and 2 μm wide trench without void formation. We also investigated the 2D doping distribution of the filled area by SSRM. As a result, it is found that the existence of a sub-trench was related to the generation of a doping distribution in the filled area. The trench filling mechanism and doping distribution are discussed.

Influence of Processing and of Material Defects on the Electrical Characteristics of SiC-SBDs and SiC-MOSFETs

The influences of processing and material defects on the electrical characteristics of large-capacity (approximately 100A) SiC-SBDs and SiC-MOSFETs have been investigated. In the case of processing defects, controlled activation annealing is the most important factor. On the other hand for material defects, the number of epitaxial defects must be decreased to zero for both SBDs and MOSFETs. The dislocation defects in SiC wafers are dangerous for the breakdown voltage of MOSFETs. However, they are not killer defects. If the epitaxial defect density is sufficiently low and the dislocation density is in the order of 10000cm-2, the long- term reliability of the gate oxide at the electric field of 3MV/cm can be guaranteed.

Determination of free carrier density in the low doping regime of 4H-SiC by Raman scattering

The free carrier concentration of n-4H-SiC was deduced by Raman spectroscopy using LO phonon plasmon coupled (LOPC) modes as a monitor band. We could determine the free carrier concentration from the reading of the peak frequency of the LOPC mode in the concentration range from 1019 down to 1016cm−3. The damping of LO phonons was evaluated as a function of the carrier concentration. Line shape analysis of the LOPC mode revealed that the damping of the LO phonon deduced from this analysis is sensitive to charged defects including ionized impurities.

Observation of Misfit Dislocations Introduced by Epi-Layer Growth on 4H-SiC

4H-SiC substrate wafers with epi-layers were observed using monochromatic synchrotron X-ray topography in grazing incidence geometries, to investigate the defects in the epi-layer. Misfit dislocations with b=+1/3[11 2 0] caused by the difference in lattice parameter between the epi-layer and the substrate were observed. The misfit dislocations are located near the interface as edge dislocations, and appear at the top surface as screw dislocations on basal planes. It was observed that more than half of them were introduced from the growing epi-layer surface. The misfit dislocations and some screw dislocations with b=+1/3[11 2 0] are observed to remain as basal plane dislocations at the surface, while other basal plane dislocations were converted to threading edge dislocations in the epi-layer.

Single photon sources in 4H-SiC metal-oxide-semiconductor field-effect transistors

We present single photon sources (SPSs) embedded in 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). They are formed in the SiC/SiO2 interface regions of wet-oxidation C-face 4H-SiC MOSFETs and were not found in other C-face and Si-face MOSFETs. Their bright room-temperature photoluminescence (PL) was observed in the range from 550 to 750 nm and revealed variable multi-peak structures as well as variable peak shifts. We characterized a wide variety of their PL spectra as the inevitable variation of local atomic structures at the interface. Their polarization dependence indicates that they are formed at the SiC side of the interface. We also demonstrate that it is possible to switch on/off the SPSs by a bias voltage of the MOSFET.

Electrically Detected ESR Study of Interface Defects in 4H-SiC Metal-Oxide-Semiconductor Field Effect Transistor

We present an electrically detected electron-spin-resonance (ESR) study on SiO2-SiC interface regions of n-channel lateral 4H-SiC MOSFETs with hydrogen annealing. This characterization technique can reveal electrically active defects that interact with channel currents of the MOSFETs. The defects were observed at 20 K, and were labeled “PH0” and “PH1”, one of which (PH1) exhibited a 1H hyperfine splitting of 5.3 mT.