Ryuichi Izawa

Impact of the gate-drain overlapped device (GOLD) for deep submicrometer VLSI

The gate-drain overlapped device (GOLD) structure is proposed to achieve high reliability and high performance in deep submicrometer MOSFETs. The GOLD device concept is different from that of drain-engineering methods such as the double-diffused drain (DDD) and lightly doped drain (LDD). GOLD eliminates the tradeoff between transconductance and breakdown voltage (hot-carrier, drain sustaining). The overlap effect of the GOLD devices is discussed using simulation and experiment. GOLD has a gate structure using a native oxide film (5-10 A) to obtain an overlapped fine structure. The process is also compatible with conventional LDD processes and is suitable for 0.3-0.5- mu m-design-rule devices at 5-V operation, and 3-V operation. >

AC hot-carrier effects in scaled MOS devices

AC hot-carrier effects with complete precautions against the wiring inductance noises were investigated to get a universal guideline from the viewpoints of AC conditions and device structures (single drain (SD), LDD, and GOLD). Pulse-induced-noises due to the wiring inductance of measurement systems screens intrinsic AC effects. After precautions against noises, AC hot-carrier degradation can be estimated in LDD on the basis of DC measurements. The noise is negligible for degradation when the wiring inductance is smaller than 250 m Omega . In terms of device structure dependence, for SD and LDD, enhanced AC degradation was observed during channel hot-electron (CHE) stress. No acceleration occurred with drain avalanche hot-carrier (DAHC). In LDD, this enhancement can be attributed to stronger DAHC stress during gate pulse transients, while in SD, trapping of channel hot electrons at neutral traps created at the rising and the falling edges of gate pulses acted as an additional acceleration factor. In the case of GOLD, however, no difference between AC and DC stress was seen for DAHC or CHE conditions, and CHE stress was more severe than DAHC stress, which was possibly due to a large gate current characteristic.<<ETX>>

The impact of N - drain length and gate&#8212;drain/source overlap on submicrometer LDD devices for VLSI

To obtain optimal values for the key factors in enchancing the reliability and performance of deep submicrometer lightly doped drain (LDD) structures, the influence of LDD device parameters-n-drain length Ln, gate-drain/source overlap length Γ, and n- dose Nd-on reliability and performance were investigated using a three-dimensional (3-D) device simulator and experiment. A new device structure is discussed as a guide for deep submicrometer LDD design. This structure makes an advantageous use of the gate-drain overlap effect without scaling of Lnand Γ.

N - source/drain compensation effects in submicrometer LDD MOS devices

N- source/drain compensation effects in LDD devices and p-n junction leakage effects are investigated. In particular, forL_{eff} \leq 0.3µm, these effects will become intrinsic constraints on device minituarization. Furthermore, p-n junction leakage was found to cause refresh failures in dynamic VLSI circuits even under reduced power supply voltage.

Substrate Engineering for VTH-Scaling at Low Supply Voltage (1.5-3 V) in ULSIs

A substrate engineering method is proposed to scale down Vrn at low supply voltage(1.5-3V) without punchthrough. This guideline results from a netr interpretation of the relationship between Vrn and nininurn channel length LEFF at which punchthrough is controlled. The most pronising punchthrough stopper should be laid in the depth between 0.05 p n and the source-drain junction depth. It results not only in suppression of punchthrough but also reduction of body effect and junction capacitance without affecting Vrn excessively. As a result, LEFF below 0.3 pm and 0.2V Vtn can be achieved sinultaneously.

AC hot-carrier degradation due to gate-pulse-induced noise

Hot-carrier degradation mechanisms under AC stress are investigated by taking into account gate-pulse-induced noise effects. It is found that the increase of AC hot-carrier degradation is due to the wiring inductance effect in ULSI circuits and in measurement systems. Except for this noise effect, other peculiar effects at the falling and/or rising edges of the gate pulse can be disregarded. As a result, the lifetime under AC stress conditions can be predicted using the DC lifetime and duty cycles. In addition, circuit impedance guidelines for suppressing induced noise are proposed, based on a detailed analysis of noise mechanisms.<<ETX>>

A New Insight into the PN-Junction Characteristics of ULSI -The Time Dependent Junction Breakdown (TDJB)-

A new concept of tine dependent junction breakdown (TDJB), which shows a close analogy with TDDB, has been proposed as a method for evaluating long-term junction reliability. This paper discusses junction reliability from the viewpoint of time dependent breakdown. In addition to the intrinsic breakdown due to avalanche phenonena, tine dependent junction b.reakdown (TDJB) has been revealed by accelerated lifetests. Intrinsic breakdown due to avalanche phenomena has been found to be caused by the electrons trapped at the perineter of the junction. These results indicate that not only oxide reliability but also junction reliability will becone a key factor in fabrication of future scaled UtSI s.