Masaharu Kubo

Characteristics and limitation of scaled-down MOSFET's due to two-dimensional field effect

Practical limitations of minimum-size MOS-LSI devices are investigated through measurement of experimental devices. It is assumed that scaled-down MOSFETs are limited by three physical phenomena. These are 1) poor threshold control which is caused by drain electric field, 2) reduced drain breakdown voltage due to lateral bipolar effects, and 3) hot-electron injection into the gate oxide film which yields performance variations during device operation. Experimental models of these phenomena are proposed and the smallest possible MOSFET structure, for a given supply voltage, is considered. It is concluded that the smallest feasible device has a channel length of 0.52 µm and a gate oxide thickness of 9.4 nm when the supply voltage is 1.5 V. Reliable threshold control is most difficult to realize in an MOS-LSI with the smallest devices.

Perspective on BiCMOS VLSIs

A high-performance BiCMOS technology (Hi-BiCMOS) and its applications to VLSIs are described. By combining bipolar and CMOS devices in unit circuits of VLSIs, Hi-BiCMOS provides both speed performance competitive with bipolar LSIs and integration density close to that of CMOS LSIs. Hi-BiCMOS technology has been successfully used for static RAMs, dynamic RAMs, and gate arrays. The effectiveness of its applications to some types of processors has also been examined by evaluating test chips. >

MOS area sensor: Part II—Low-noise MOS area sensor with antiblooming photodiodes

The development of a high-sensitivity 320 × 244 element MOS area sensor and a novel fixed pattern noise (FPN) suppressing circuit are reported in this paper. The new device incorporates p+-n+high-C photodiodes and double-diffused sense lines. The p+-n+high-Cphotodiodes provide a large dynamic range and a large saturation signal of 1.4 µA with 6-1x W-lamp illumination. The double-diffused sense lines are introduced to vastly improve blooming characteristics, making use of a built-in potential barrier. FPN is proved to stem mainly from inversion charge variations through horizontal switching MOS gate capacitances. A simple high-performance FPN suppressing circuit is proposed which realizes high signal-to-noise (S/N) ratios of more than 68 dB at saturation. The new sensor is tested in a high-sensitivity black-and-white VTR hand-held camera and will find broad applications.

MOS area sensor: Part I—Design consideration and performance of an n-p-n structure 484 × 384 element color MOS imager

The design consideration and performance of an n-p-n structure 484 × 384 element MOS imager is described. The imager has a photodiode array and scanners separately integrated on different p wells. The horizontal scanner, consisting of bootstrapping type noninverting circuits, features high speed and low noise. The maximum scan rate of the scanner is ∼15 MHz. The vertical scanner, consisting of inverting circuits, has a wide dynamic operating range. It can operate stably under an intense illumination of ∼ 1500 1x. Analysis of the MOS switch with a photodiode is also carried out. The 484 × 384 imager has shown excellent performances: signal to fixed-pattern-noise ratio of 54 dB, horizontal resolution of 260 TV lines, vertical resolution of 350 TV lines, well-balanced spectral response, and antiblooming.

A high power MOSFET with a vertical drain electrode and a meshed gate structure

A MOSFET with a maximum power of 200 W in a 5/spl times/5 mm/SUP 2/ chip which exhibits 20-A current, 3000-millimho transconductance and 100-V breakdown voltage has been developed. The features of the device structure are a vertical drain electrode which makes it possible to use most of the surface area for the source electrode, and a meshed gate structure which realizes an increase in the channel width per unit area. The p-channel device with an offset gate structure was fabricated from an n on p/SUP +/ epitaxial wafer by using polysilicon gate and ion implantation processes. The device can be operated stably at ambient temperatures up to 180/spl deg/C. While the bipolar transistor is a suitable power device in the low voltage region, the MOSFET looks more promising in the high voltage region than the V-FET and the bipolar transistor.

2/3-inch format MOS single-chip color imager

A new 2/3 format MOS single-chip color imager, that includes 384 × 485 elements, has been developed. The device features a low-noise design; high sensitivity (9 nApp/lx for 2855 K W lamp), through employment of a complementary color filter; and wide dynamic range (over 60 dB), through introduction of a p+-layer in the photodiode and a vertical buffer circuit. The imager also features low aliasing (Moire) and clear color due to the use of a new color filter arrangement and unique multivideo lines. The die measures 10.0mm × 8.5 mm, which is realized using standard 3-µm Si-gate MOSLSI technology. Combining this small size and technological simplicity with on-wafer color filter processing, has made this device suitable for LSI volume production.

An NPN structure 484×384 MOS imager for a single-chip color camera

An MOS imager featuring an NPN structure for anti blooming and built-in double video lines for color signal pickup will be described. Imager is used in single-chip color camera with TV resolution.

A threshold voltage controlling circuit for short channel MOS integrated circuits

A threshold stabilizing circuit which controls substrate of short channel (2 μm) MOS-ICs by negative-feedback, will be described. Operating range of VDD(1.5 to 8V) is free from threshold fluctuations.

A high-speed low-power Hi-CMOS 4K static RAM

A high-speed low-power CMOS fully static, 4096 word by 1 bit random-access memory (RAM) has been developed, which contains a bipolar-CMOS (BCMOS) circuit on the same chip. The device is realized using low-power-oriented circuit design and high-performance CMOS technology utilizing 3-µm gate length. The fabricated 4K static RAM has an address access time of 43 ns and a power dissipation of 80 mW.

Fault tolerant techniques for memory components

Both manufacturers and users of memory components now accept the use of redundancy to improve yields. Currently, the most common practice is to replace defective elements by programming fusible links. As memory densities increase and device physics contraints become more severe, fault tolerant techniques are likely to diversify. For example, on-chip error correction has been employed to correct both hard defects and soft errors. The alternative fault tolerant techniques, their merits and limitations, and their impact on the characteristics of future memory components will be discussed.