S. Bettarini

Development of deep N-well MAPS in a 130 nm CMOS technology and beam test results on a 4k-pixel matrix with digital sparsified readout

We report on further developments of our recently proposed design approach for a full in-pixel signal processing chain of deep n-well (DNW) MAPS sensors, by exploiting the triple well option of a CMOS 0.13 μm process. The optimization of the collecting electrode geometry and the re-design of the analog circuit to decrease power consumption have been implemented in two versions of the APSEL chip series, namely “APSEL3T1” and “APSEL3T2”. The results of the characterization of 3x3 pixel matrices with full analog output with photons from 55Fe and electrons from 90Sr are described. Pixel equivalent noise charge (ENC) of 46 e- and 36 e- have been measured for the two versions of the front-end implemented toghether with signal-to-noise ratios between 20 and 30 for Minimum Ionizing Particles. In order to fully exploit the readout capabilities of our MAPS, a dedicated fast readout architecture performing on-chip data sparsification and providing the timing information for the hits has been implemented in the prototype chip “APSEL4D”, having 4096 pixels. The criteria followed in the design of the readout architecture are reviewed. The implemented readout architecture is data-driven and scalable to chips larger than the current one, which has 32 rows and 128 columns. Tests concerning the functional characterization of the chip and response to radioactive sources have shown encouraging preliminary results. A successful beam test took place in September 2008. Preliminary measurements of the APSEL4D charge collection efficiency and resolution confirmed the DNW device is working well. Moreover the data driven approach of the readout chips has been successfully used to demonstrate the possibility to build a Level 1 trigger system based on Associative Memories.

Proposal of a data sparsification unit for a mixed-mode MAPS detector

The Italian silicon-detectors-with-low-interaction-with material collaboration (SLIM5) has designed, fabricated and tested several prototypes of CMOS monolithic active pixel sensors (MAPS). This paper shows the design of a new mixed-mode chip prototype composed of a bidimensional matrix of pixels, and of an off-pixel digital readout sparsification circuit. The readout logic is based on commercial standard cells and implements an optimized non token readout technique. Also, a MAPS emulator software toool is presented. The project is aimed at overcoming the readout speed limit of future large-matrix pixel detectors for particle tracking, by matching the requirements of future high-energy physics experiments. The readout architecture extends the flexibility of the MAPS devices to be also used in first level triggers on tracks in vertex detectors.

Recent development on triple well 130 nm CMOS MAPS with in-pixel signal processing and data sparsification capability

A different approach to the design of CMOS MAPS has recently been proposed. By exploiting the triple well option of a CMOS commercial process, a deep n-well (DNW) MAPS sensor has been realized with a full in-pixel signal processing chain: charge preamplifier, shaper, discriminator and a latch. This readout approach beeing compatible with data sparsification will improve the readout speed potential of MAPS sensors. The first protoype chips, realized with STMicroelectronics 130 nm triple well process, proved the new design proposed for DNW MAPS is viable with a good sensitivity to photons from 55Fe and electrons from 90Sr. Extensive tests performed to characterize the second generation of the APSEL chips based on the DNW MAPS design are reported. Small 3times3 pixel matrices with full analog output have been tested with radioactive sources to characterize charge collection. Pixel noise equivalent charge (ENC) of 50 e- and signal-to-noise ratio for MIPs of about 14 have been measured. Improved pixel noise and reduced threshold dispersion (about 100 e-) have been measured in the 8times8 matrix with a sequential readout. Based on the new DNW MAPS design a dedicated fast readout architecture to perform on-chip data sparsification is currently under development. The aim is to incorporate in the same detector the advantages of the thin CMOS sensors and similar functionalities as in hybrid pixels.

Development of 130nm CMOS Monolithic Active Pixels with In-pixel Signal Processing

We developed monolithic active pixel detectors that exploit the triple well option of CMOS 130 nm technology to implement analog and digital signal processing at the pixel level. The charge collecting element is realized using the deep N-well (DNW) and partially overlaps the analog circuit. With this scheme we were able to implement a full in-pixel signal processing chain, composed of a charge preamplifier, shaper, discriminator, and latch. This approach has been validated by a first prototype (APSEL0), and we report here on the extensive measurements performed on the second prototype (APSEL1), containing various single pixel structures with analog readout and an 8 times 8 matrix of 50 times 50 mum2 pixels with sequential digital readout. For 900 mum2 pixels the equivalent noise charge has been measured to be 40 e-, with a S/N ratio of about 30 for the 55Fe 5.9 keV signal. The matrix readout has been tested up to 30 MHz and the crosstalk between pixels characterized. The threshold dispersion and the noise of the pixels in the matrix have been measured through noise scans. These measurements confirm the viability of the triple well process for MAPS fabrication, and indicate the design improvements for the next prototype chip (APSEL2).

Triple Well CMOS Active Pixel Sensor with In-Pixel Full Signal Analog

We report on a new approach in the design of CMOS monolithic active pixel sensor (MAPS). We realized a first MAPS prototype chip implementing at the pixel level the standard processing chain commonly used for capacitive detectors. The in-pixel signal processing channel includes a low noise charge preamplifier, a shaper, a discriminator and a latch. This readout approach, realized exploiting the triple well option available in the 0.13 mum process by STMicrolectronics, is compatible with already available architectures performing data sparsification at the pixel level. This feature will be implemented in future development of our device to improve the readout speed potential of these sensors with respect to existing MAPS. Using a charge preamplifier to perform charge to voltage conversion, we also extended the area of the sensing electrode to increase the signal collected by a single pixel. The first prototype chips have been successfully tested with very encouraging results. In this paper we summarize the performance of the front-end electronics and present the response of the sensor to ionizing radiation

2D and 3D thin pixel technologies for the Layer0 of the SuperB Silicon Vertex Tracker

The high luminosity asymmetric e+e− collider SuperB, recently approved by the Italian Government, is designed to deliver a luminosity greater than 1036cm−2s−1 with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. An improved vertex resolution is required for precise time-dependent measurements and the SuperB Silicon Vertex Tracker will be equipped with an innermost layer of small radius (about 1.5 cm), resolution of 10 µm in both coordinates, low material budget (< 1% X0), and able to withstand a hit background rate of several tens of MHz/cm2. The ambitious goal of designing a thin pixel device matching these stringent requirements is being pursued with specific R&D programs on different technologies: CMOS MAPS, pixel sensors in vertical integration technology and hybrid pixels with small pitch and reduced material budget. The latest results on the characterization of the various pixel devices realized for the SuperB Layer0 will be presented.

Study of the radiation hardness of irradiated AToM front-end chips of the BaBar silicon vertex tracker

The radiation hardness of the AToM chips of the BaBar silicon vertex tracker has been investigated by means of irradiations with photons from a Co60 source and 0.9 GeV electrons. The increase in noise and the decrease in gain of the amplifier have been measured as a function of the applied capacitive load and the absorbed dose. Different beam intensities have been used to study the effect of different dose rates to the AToM radiation damage. The chip digital functionalities have been tested up to a dose of 5.5 Mrads for the Co60 photons and 9 Mrads for the 0.9 GeV electrons. In addition a pedestal shift for the irradiated channels has been observed in the test with electrons but is not present in the irradiation with photons. This effect reproduces qualitatively the behavior observed since 2002 in the front-end electronics of the installed BaBar silicon vertex tracker. After some investigation of the chip layout, this peculiar behavior could be associated to radiation damage in a well-identified component of the AToM. The results of the radiation tests are presented and used to extrapolate the performance and lifetime of the installed detector in the next few years.

On-Chip Fast Data Sparsification for a Monolithic 4096-Pixel Device

The paper describes a mixed-mode ASIC composed of a fast readout architecture that interfaces with a matrix of 4096 Monolithic Active Pixel Sensors (MAPS). The matrix has 128 columns and 32 rows of pixels and is divided into 256 regions of 4 times 4 pixels, named macro-pixels (MPs). The chip is an upgrade of a smaller version having 256 pixels that was designed and tested. The two chips were designed via STM 130 nm CMOS technology. The pixel dimension is 50 by 50 mum2 . The work is aimed at improving the design of MAPS detectors with an on-chip fast sparsification system, for particle tracking, to match the requirements of future high-energy physics experiments. The readout architecture implemented is data driven to extend the flexibility of the system, to be also used in first level triggers on tracks in vertex detectors. Simulations indicate that the readout system can cope with an average hit rate up to 100 MHz/cm2 if a master clock of 80 MHz is used, while maintaining an overall efficiency over 99%.

High-gain bipolar phototransistor on high-resistivity silicon substrate: a new device for the detection of ionizing radiation

NPN bipolar phototransistors have been designed and fabricated on high-resistivity silicon substrates of different thicknesses, up to 800 /spl mu/m. A technology featuring a double implant for the emitter allowed us to obtain a typical current gain of about 600. The device has been used to detect /spl alpha/ particles from a /sup 239/Pu source, /spl beta/ particles from /sup 90/Sr and X-rays from /sup 241/Am using a simple experimental set-up, by directly connecting the detector to the scope. In the case of electrons, typical pulse heights of 100 mV have been observed, with pulse length of 50/spl mu/s, measured on a load resistor in series to the emitter. The parameters driving the time performance have been measured, obtaining a good agreement with the electrical model of the device. We report on the functional characterization of the device with emphasis on the energy calibration and the electronic noise measurement.

Monolithic pixel sensors for fast particle trackers in a quadruple well CMOS technology

The Apsel4well monolithic active pixel sensor (MAPS) chip prototype is meant as an upgrade solution for the Layer0 of the SuperB silicon vertex tracker. The design is based on a 180 nm CMOS process with quadruple well called INMAPS. This technology makes it possible to overcome the main drawbacks related to three transistors MAPS. Moreover, the presence of a high resistivity epitaxial layer is expected to lead to further improvements in terms of charge collection performance and radiation resistance. This paper, after giving some hints on the INMAPS process, focuses on the analog front-end section of the pixel readout chain. Measurement results on the main analog channel performance, like charge sensitivity and equivalent noise charge, are given along with charge collection efficiency evaluation through laser stimulation. These last characterization data were also used for validating TCAD simulation results of the sensor charge collection performance. Finally, results from a neutron irradiation campaign performed with fluences up to 2.7 × 1013 1 MeV neutron equivalent/cm2 will be shown and compared with the outcome of a Monte Carlo charge loss model of the structure useful for the rad-harder design of the next quadruple well MAPS.