S. Bonacini

The GBT Project

The GigaBit Transceiver (GBT) architecture and transmission protocol has been proposed for data transmission in the physics experiments of the future upgrade of the LHC accelerator, the SLHC. Due to the high beam luminosity planned for the SLHC, the experiments will require high data rate links and electronic components capable of sustaining high radiation doses. The GBT ASICs address this issue implementing a radiation-hard bi-directional 4.8 Gb/s optical fibre link between the counting room and the experiments. The paper describes in detail the GBT-SERDES architecture and presents an overview of the various components that constitute the GBT chipset.

The GBT-SerDes ASIC prototype

In the framework of the GigaBit Transceiver project (GBT), a prototype, the GBT- SerDes ASIC, was developed, fabricated and tested. To sustain high radiation doses while oper- ating at 4.8Gb/s, the ASIC was fabricated in a commercial 130 nm CMOS technology employing radiation tolerant techniques and circuits. The transceiver serializes-deserializes the data, Reed- Solomon encodes and decodes the data and scrambles and descrambles the data for transmission over optical fibre links. This paper describes the GBT-SerDes architecture, and presents the test results.

Characterization of a commercial 65 nm CMOS technology for SLHC applications

The radiation characteristics with respect to Total Ionizing Dose (TID) and Single-Event Upsets (SEUs) of a 65 nm CMOS technology have been investigated. Single transistor structures of a variety of dimensions and several basic circuits were designed and fabricated. The circuits include a 64-kbit shift-register, a 56-kbit SRAM and a ring-oscillator. The test chips were irradiated up to 200 Mrad with an X-ray beam and the corresponding transistor threshold shifts and leakage currents were measured. Heavy-ion beam irradiation was performed to assess the SEU sensitivity of the digital parts. Overall, our results give the confidence that the chosen 65 nm CMOS technology can be used in future High Energy Physics (HEP) experiments even without Hardness-By-Design (HBD) solutions, provided that constant monitoring of the TID response is carried out during the full manufacturing phase of the circuits.

The GBT-SCA, a radiation tolerant ASIC for detector control and monitoring applications in HEP experiments

The future upgrades of the LHC experiments will increase the beam luminosity leading to a corresponding growth of the amounts of data to be treated by the data acquisition systems. To address these needs, the GBT (Giga-Bit Transceiver optical link [1,2]) architecture was developed to provide the simultaneous transfer of readout data, timing and trigger signals as well as slow control and monitoring data. The GBT-SCA ASIC, part of the GBT chip-set, has the purpose to distribute control and monitoring signals to the on-detector front-end electronics and perform monitoring operations of detector environmental parameters. In order to meet the requirements of different front-end ASICs used in the experiments, it provides various user-configurable interfaces capable to perform simultaneous operations. It is designed employing radiation tolerant design techniques to ensure robustness against SEUs and TID radiation effects and is implemented in a commercial 130 nm CMOS technology. This work presents the GBT-SCA architecture, the ASIC interfaces, the data transfer protocol, and its integration with the GBT optical link.

A prototype hybrid pixel detector ASIC for the CLIC experiment

A prototype hybrid pixel detector ASIC specifically designed to the requirements of the vertex detector for CLIC is described and first electrical measurements are presented. The chip has been designed using a commercial 65 nm CMOS technology and comprises a matrix of 64 × 64 square pixels with 25 μm pitch. The main features include simultaneous 4-bit measurement of Time-over-Threshold (ToT) and Time-of-Arrival (ToA) with 10 ns accuracy, on-chip data compression and power pulsing capability.

E-link : A Radiation-Hard Low-Power Electrical Link for Chip-to-Chip Communication

The e-link, an electrical interface suitable for transmission of data over PCBs or electrical cables, within a distance of a few meters, at data rates up to 320 Mbit/s, is presented. The elink is targeted for the connection between the GigaBit Transceiver (GBTX) chip and the Front-End (FE) integrated circuits. A commercial component complying with the Scalable LowVoltage Signaling (SLVS) electrical standard was tested and demonstrated a performance level compatible with our application. Test results are presented. A SLVS transmitter/receiver IP block was designed in 130 nm CMOS technology. A test chip was submitted for fabrication.

An SEU-Robust Configurable Logic Block for the Implementation of a Radiation-Tolerant FPGA

Within the perspective of the development of a radiation-tolerant SEU-robust reprogrammable FPGA, a user-configurable Logic Block was designed in a CMOS 0.25 mum technology. The configuration bits are stored in SEU-robust registers as well as the user data. The design takes care of minimizing the possibility of SET coming from the combinatorial logic. The Logic Block can implement any boolean expression of 4 variables, has a carry propagation infrastructure and a user-register. A set of Logic Blocks can be organized to form more complex logic functions. A test chip was fabricated and tested in a heavy-ion beam facility. Testing demonstrated the SEU robustness of the circuit up to an LET of 79.6 cm2 MeV/mg and a small sensitivity at higher LETs

1-Grad total dose evaluation of 65 nm CMOS technology for the HL-LHC upgrades

The radiation tolerance of 65 nm bulk CMOS devices was investigated using 10 keV X-rays up to a Total Ionizing Dose (TID) of 1 Grad. Irradiation tests were performed at room temperature (25°C) as well as at low temperature (−15°C). The implications on the DC performance of n and p channel transistors are presented. For small size devices, a strong performance degradation is observed from a dose of 100 Mrad. Irradiations made at room temperature up to 1 Grad show a complete drive loss in PMOS devices, due to decreasing transconductance. When the irradiation is conducted at −15°C, the devices show less radiation damage. Annealing helps recovering a small part of the drive capabilities of the small size devices, but the threshold voltage shift is still high and might compromise the operation in some digital applications.

A lossless data compression system for a real-time application in HEP data acquisition

This paper presents a compression system optimized for the reduction of data from pulse digitizing electronics.

A 20 mW, 4.8 Gbit/sec, SEU robust serializer in 65nm for read-out of data from LHC experiments

The availability of a sub 1-W SerDes for future LHC read-out systems is of paramount importance for building new low-mass inner detectors for HL-LHC. This work reports on the design of two alternative architectures for the serializer block within a high speed transmitter with the objective of achieving a power consumption of less than 30 mW at the operating speed of 4.8 Gbit/sec. Two alternative architectures are implemented using a commercial 65nm LP-CMOS technology. The architectures used are a simple TMR and a code-protected one, and are meant to investigate different strategies to handle SEUs. While using the same technology and flip-flops, the simple TMR architecture results in a consumption of 30 mW, the code-protected one of 19 mW, which are better than 1/4 of the power used in state-of-the-art rad-hard serializers. Early data on robustness to SEU effects are also presented.