S. Dinesh Kumar

Energy-Efficient and Secure S-Box Circuit Using Symmetric Pass Gate Adiabatic Logic

Differential Power Analysis (DPA) attack is considered to be a main threat while designing cryptographic processors. In cryptographic algorithms like DES and AES, S-Box is used to indeterminate the relationship between the keys and the cipher texts. However, S-box is prone to DPA attack due to its high power consumption. In this paper, we are implementing an energy-efficient 8-bit S-Box circuit using our proposed Symmetric Pass Gate Adiabatic Logic (SPGAL). SPGAL is energy-efficient as compared to the existing DPA-resistant adiabatic and non-adiabatic logic families. SPGAL is energy-efficient due to reduction of non-adiabatic loss during the evaluate phase of the outputs. Further, the S-Box circuit implemented using SPGAL is resistant to DPA attacks. The results are verified through SPICE simulations in 180nm technology. SPICE simulations show that the SPGAL based S-Box circuit saves upto 92% and 67% of energy as compared to the conventional CMOS and Secured Quasi-Adiabatic Logic (SQAL) based S-Box circuit. From the simulation results, it is evident that the SPGAL based circuits are energy-efficient as compared to the existing DPA-resistant adiabatic and non-adiabatic logic families. In nutshell, SPGAL based gates can be used to build secure hardware for low power portable electronic devices and Internet-of-Things (IoT) based electronic devices.

QUALPUF: A Novel Quasi-Adiabatic Logic based Physical Unclonable Function

In the recent years, silicon based Physical Unclonable Function (PUF) has evolved as one of the popular hardware security primitives. PUFs are a class of circuits that use the inherent variations in the Integrated Circuit (IC) manufacturing process to create unique and unclonable IDs. There are various security related applications of PUFs such as IC counterfeiting, piracy detection, secure key management etc. In this paper, we are presenting a novel QUasi-Adiabatic Logic based PUF (QUALPUF) which is designed using energy recovery technique. To the best of our knowledge, this is the first work on the hardware design of PUF using adiabatic logic. The proposed design is energy efficient compared to recent designs of hardware PUFs proposed in the literature. Further, we are proposing a novel bit extraction method for our proposed PUF which improves the space set of challenge-response pairs. QUALPUF is evaluated in security metrics including reliability, uniqueness, uniformity and bit-aliasing. Power and area of QUALPUF is also presented. SPICE simulations show that QUALPUF consumes 0.39μ Watt of power to generate a response bit.

Adiabatic Computing Based Low-Power and DPA-Resistant Lightweight Cryptography for IoT Devices

Internet of Things (IoT) devices are mostly small and operate wirelessly on limited battery supply, and therefore have stringent constraints on power consumption and hardware resources. Lightweight cryptography (LWC) provides cryptographic solutions for resource-constrained IoT devices. LWC based IoT devices are vulnerable to side-channel attacks such as Differential Power Analysis (DPA). The existing CMOS-based countermeasures for DPA are not suitable for circuits working under energy constraints. Adiabatic logic is one of the promising computing paradigms to design energy-efficient and DPAresistant hardware. Therefore, we have investigated the usefulness of adiabatic logic for low-power and DPA-resistant LWC for IoT devices. In this paper, the PRESENT-80 LWC algorithm is used as a benchmark circuit. The PRESENT-80 algorithm is implemented using Symmetric Pass Gate Adiabatic Logic (SPGAL). SPICE simulations at 12.5 MHz validated that one round of PRESENT-80 implemented using SPGAL gates saves 83% and 91% of power consumption in comparison to CMOS and SABL (Sense Amplifier Based Logic) based implementations, respectively. The security of SPGAL based PRESENT-80 has been evaluated by performing a DPA attack through SPICE simulations. We proved that the SPGAL-based implementation of the PRESENT-80 algorithm is resistant to DPA attacks. Further, low-leakage nano-electronic device FinFET can provide powerefficient solutions for IoT devices. Therefore, the design of the PRESENT-80 algorithm using FinFET based SPGAL gates is also presented. The simulations proved that adiabatic FinFET circuits consume low-power and are more resistant to DPA attacks as compared to adiabatic CMOS circuits.

UTB-SOI based adiabatic computing for low-power and secure IoT devices

Adiabatic logic is one of the promising computing paradigm to design energy-efficient and Differential Power Analysis (DPA)-resistant hardware. However, CMOS based adiabatic logic suffers from high leakage power. In order to reduce the leakage power in the existing DPA-resistant adiabatic logic families, we are investigating the usefulness of Ultra-Thin-Body Silicon-On-Insulator (UTB-SOI) devices as the replacement of CMOS devices. As a case study, we have implemented the PRESENT-80 Light Weight Cryptography (LWC) algorithm in UTB-SOI based Symmetric Pass Gate Adiabatic Logic (SPGAL). The security of UTB-SOI SPGAL based PRESENT-80 has been evaluated by performing a DPA attack through SPICE simulations. We proved that the UTB-SOI SPGAL implementation of the PRESENT-80 algorithm is resistant to DPA attacks. SPICE simulations show that the consumption of leakage power for UTB-SOI SPGAL XOR gate is 60% less in comparison to CMOS SPGAL XOR gate. It is also shown that, one round of PRESENT-80 simulated using UTB-SOI SPGAL consumes 36% less power in comparison to CMOS SPGAL one round of PRESENT-80.

FinSAL: A novel FinFET based Secure Adiabatic Logic for energy-efficient and DPA resistant IoT devices

With the emergence of Internet of Things (IoT), there is an urgent need to design energy-efficient and secure IoT devices. For example, IoT devices such as Radio Frequency Identification (RFID) tags and Wireless Sensor Nodes (WSN) employ AES cryptographic modules that are susceptible to Differential Power Analysis (DPA) attacks. With the scaling of technology, leakage power in the cryptographic devices increases, which increases the vulnerability to DPA attacks. This paper presents a novel FinFET based Secure Adiabatic Logic (FinSAL), that is energy-efficient and DPA-immune. The proposed adiabatic FinSAL is used to design logic gates such as buffers, XOR, and NAND. Further, the logic gates based on adiabatic FinSAL are used to implement a Positive Polarity Reed Midler (PPRM) architecture based S-box circuit. SPICE simulations at 12.5 MHz show that adiabatic FinSAL S-box circuit saves up to 84% of energy per cycle as compared to the conventional S-box circuit implemented using FinFET. Further, the security of adiabatic FinSAL S-box circuit has been evaluated by performing the DPA attack through SPICE simulations. We proved that the FinSAL S-box circuit is resistant to a DPA attack through a developed DPA attack flow applicable to SPICE simulations.

EE-SPFAL: A Novel Energy-Efficient Secure Positive Feedback Adiabatic Logic for DPA Resistant RFID and Smart Card

The emergence of Internet of Things (IoT) have increased the need of Radio Frequency Identification (RFID) and smart cards that are energy-efficient and secure against Differential Power Analysis (DPA) attacks. Adiabatic logic is one of the circuit design techniques that can be used to design energy-efficient and secure hardware. However, the existing DPA resistant adiabatic logic families suffer from non-adiabatic energy loss. Therefore, this work presents a novel adiabatic logic family called Energy-Efficient Secure Positive Feedback Adiabatic Logic (EE-SPFAL) family that reduces the non-adiabatic energy loss and also is secure against DPA attacks. The proposed EE-SPFAL is used to design logic gates such as buffers, XOR, and NAND. Further, the logic gates based on EE-SPFAL are used to implement a Positive Polarity Reed Muller (PPRM) architecture based S-box circuit. SPICE simulations at 12.5 MHz show that EE-SPFAL based S-box circuit saves up to 65 percent of energy and 90 percent of energy per cycle as compared to the S-box circuit implemented using existing Secured Quasi-Adiabatic Logic (SQAL) and conventional CMOS logic, respectively. Further, the security of EE-SPFAL based S-box circuit has been evaluated by performing the DPA attack through SPICE simulations. We proved that the EE-SPFAL based S-box circuit is resistant to a DPA attack through a developed DPA attack flow applicable to SPICE simulations. Further, we have implemented the one round of Advanced Standard Encryption (AES) algorithm and we found that one round of EE-SPFAL logic based AES consumes uniform current with different input plain texts. Low energy consumption and security against DPA attacks makes EE-SPFAL logic a suitable candidate to implement in IoT devices such as RFID and smart cards.