S.J. Daubert
Bell Labs
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Featured researches published by S.J. Daubert.
international symposium on circuits and systems | 1989
David Gerard Vallancourt; Yannis Tsividis; S.J. Daubert
A method for making practically identical copies of a sampled current without relying on the matching of circuit elements (such as capacitors or transistors) is presented. Compact circuit realizations are discussed, leading to the generation of a family of analog function blocks for the creation, copying, and manipulation of current samples, all free from dependency on element matching. Applications of these circuits include signal processors and A/D (analog-to-digital) and D/A (digital-to-analog) convertors.<<ETX>>
custom integrated circuits conference | 1991
S.J. Daubert; David Gerard Vallancourt
Current-copier circuits are used in the IC realization of a transistor-only second-order Sigma Delta modulator fabricated in a 0.9- mu m digital CMOS process. The 13-bit resolution and 12-bit full-scale linearity make the converter suitable for A/D conversion in high-performance telecommunications applications.<<ETX>>
IEEE Journal of Solid-state Circuits | 1989
S.J. Daubert; D.W. Green; John M. Khoury; J.M. Trosino; E.J. Zimany; J.R. Barner; J. Plany; M.F. Tompsett
A mixed analog/digital chip that forms the core of a medium-speed modem for use on the public switched telephone network is described. It meets CCITT and AT&T requirements for data transmission at 2400 and 1200 b/s, and the AT&T requirement for 300-b/s operation. The chip is implemented in a 1.75- mu m analog CMOS process and occupies 32.4 mm/sup 2/. The device is powered by a single +5-V supply and consumes less than 115 mW. The architecture and circuit implementation are described, and experimental results are given. >
custom integrated circuits conference | 1988
S.J. Daubert; D.W. Green; J.M. Khoury; J.M. Trosino; E.J. Zimany; J.R. Barner; J. Plany; M.F. Tompsett
A description is given of a mixed analog/digital chip that forms the core of a low-speed modem for use over standard telephone lines. It meets CCITT and AT&T requirements for data transmission at 1200 and 2400 b/s and the AT&T requirements for 300-b/s operation. The chip is implemented in a 1.75- mu m analog CMOS process and occupies 32.4 mm/sup 2/. The device is powered by a single +or-5-V supply and consumes less than 115 mW. The architecture and circuit implementation are described, and experimental results are given.<<ETX>>
Electronics Letters | 1988
S.J. Daubert; David Gerard Vallancourt; Yannis Tsividis
Archive | 1994
Francis Raymond Ashley; S.J. Daubert
IEE Proceedings G Circuits, Devices and Systems | 1990
S.J. Daubert; David Gerard Vallancourt
Archive | 1984
S.J. Daubert
Archive | 1993
S.J. Daubert
Archive | 1993
David Gerard Vallancourt; S.J. Daubert