M.F. Tompsett

Charge-coupled imaging devices: Experimental results

The design and fabrication of a 96-element 3-phase linear charge-coupled device are described. A transfer efficiency of ∼95 percent over 288 transfers at a 1-MHz clock rate was measured. The use of the device as an analog delay line is demonstrated and its imaging properties are illustrated with reproductions of black and white text and a picture with gray scale. The results demonstrate the feasibility of using self-scanned imaging devices in practical applications. Configurations are presented for both an improved linear and an area imaging device. In both cases the problem of image smear, which occurs if stored charge is transferred along the light-sensitive region and if significant light integration takes place during this transfer, can be avoided.

The quantitative effects of interface states on the performance of charge-coupled devices

The several effects of interface states in limiting the performance of surface channel charge-coupled devices (CCDs) are described and evaluated. The limitations on transfer efficiency may be minimized by using a background charge in the device at all times. Experimental measurements of transfer inefficiency on three-phase devices and a two-phase device are presented and correlated with the predicted values, although measurements of the density and capture cross sections of interface states after device fabrication are required for accurate quantitative predictions of transfer inefficiencies. It is concluded that trapping effects are a limitation on the transfer efficiencies obtainable in surface channel charge-coupled devices, particularly, for example, at frequencies less than 1 MHz for devices having 10-µm-long transfer electrodes, but are not a direct limitation on the high-frequency performance. The effect of interface states in adding transfer noise onto the charge packets is also described, and is shown to be small, although in some devices it may reduce the signal-to-noise ratios that might otherwise be possible.

Charge-coupled imaging devices: Design considerations

In this paper some of the parameters relevant to the design of charge-coupled imaging devices are considered. Among these are charge storage capability, transfer efficiency, charge conservation, dark current, and the anticipated signal-to-noise ratio. Each is discussed, and the resultant effects on the performance of imaging devices are investigated.

Charge-coupled area image sensor using three levels of polysilicon

Charge-coupled area image sensors with 220 by 256 cells have been built using a three-phase overlapping electrode structure. Each of the three sets of electrodes is formed in a separate level of polysilicon which are isolated from each other by a thermally grown oxide, This approach relaxes the demands on mask making and photolithography that would otherwise be necessary and reduces the incidents of fatal shorts that render devices inoperable. The overlapping electrode structure results in stable performance and good transfer efficiency. The semitransparent polysilicon electrodes make the device usable with circuit side illumination although the spectral response is not very uniform. Average quantum efficiency in the visible part of the spectrum is 0.25. Measured resolution limits are 110 line pairs horizontally and 100 pairs vertically in accordance with present day PICTUREPHONE® specifications.

A three-level metallization three-phase CCD

A new electrode structure for CCDs is described. This structure is three-phase with three levels of metal and considerably relaxes the demands on the photolithography. It is predicted and shown that this structure leads to devices with a high performance, a high packing density, and a high yield over very large areas. Devices with 256 and 64 elements, primarily intended for analog delay applications, have been fabricated and measured. Transfer inefficiencies of 5 × 10-5with only 5-percent background charge and a transfer noise corresponding to an interface state density in the low 109cm-2eV-1have been measured in a surface channel device. The devices may be satisfactorily operated at pulse voltages of a few volts. In bulk channel devices, transfer ineffciencies of 2.5 × 10-5have been observed, and bulk state densities of 2 × 1011cm-3have been derived.

A charge-coupled area image sensor and frame store

A two-dimensional three-phase charge-coupled array with 128 × 106 elements, that can serve either as a solid-state image sensor or as an analog serial memory, has been built. As an image sensor the device has been operated successfully in the frame transfer mode to yield 120 frames/s with 64 × 106 resolution elements. By using the whole array as an image sensor, pictures with 128 × 106 resolution elements have been obtained at 15 frames/s with tolerable smearing. In the memory mode the device can store a whole analog frame as produced by a companion device, or 13 568 bits of digital information. But for the latter application defect-free devices are mandatory. The design of the device, the various modes of operation, the quality of the results, some typical defects, and some further applications are discussed.

Self-contained charge-coupled split-electrode filters using a novel sensing technique

Self-contained single-chip charge-coupled split-electrode filters with 55 taps and a novel channel structure have been built with a double-level polysilicon NMOS process. Operating at a sample rate of 32 kHz, these devices provide a low-pass filter function with a passband from 0 to 3.2 kHz and a stopband above 4 kHz. The image charge on the sense electrodes is detected with a novel sensing circuit employing two on-chip operational amplifiers, one of which suppresses the common-mode signal on the two sense buses while the other one integrates the difference signal. In addition, the chips carry antialiasing prefilters, a correlated double sample-and-hold circuit to minimize reset noise and to restore the output signal, and all the necessary peripheral logic and biasing circuitry so that the devices can be operated from a single master clock and two power supplies of +12 and -5 V, respectively.

A pyroelectric thermal imaging camera tube

This paper proposes the use of a thin slice of a pyroelectric single crystal as the target of an electron beam scanned camera tube. This target would be sensitive to thermal images generated by black body radiation. It is shown that 104resolvable picture points per cm2of a TGS target at a frame rate not lower than 10 Hz and a thermal resolution of 1°C in the scene should be obtainable. A pyroelectric thermal imaging camera tube based on these principles has been built and its operation will be described elsewhere [1].

A symmetrically balanced linear differential charge-splitting input for charge-coupled devices

A new charge input scheme for charge-coupled devices is described. Charge packets of a fixed size are produced in each clock cycle. Each charge packet is subsequently split into two parts under two input gates. The difference between the two resulting fractional charge packets is a linear function of the potential difference between the two signal input gates. This input scheme is particularly suitable for use with differential charge-coupled delay lines, since the charge representation of the input signal and its complement are produced in a highly symmetrical manner. The principle may also be used for splitting charge packets in any required ratio for more general application.

A dual-differential analog shift register with a charge-splitting input and on-chip peripheral circuits

A very high degree of stability and the elimination of external support circuitry are requirements for many signal-processing applications of analog charge-coupled devices. A device that meets these requirements has been designed and fabricated. The device requires a single clock input signal and achieves a gain-temperature stability of /spl plusmn/0.015 dB over 0-50/spl deg/C and a gain-voltage stability of /spl plusmn/0.05 dB over a power-supply variation of /spl plusmn/10 percent. The NMOS device demonstrates the compatibility of digital, linear, and charge-coupled devices on a single chip.