S.J. Hillenius

A symmetric submicron CMOS technology

A CMOS process is described that is designed to optimize the transistor characteristics of the n-channel and p-channel devices simultaneously. This is achieved by making the n- and p-channel devices symmetric in channel doping, junction depths, sheet resistivities and threshold voltages. The resulting devices have CoSi2source/drains with sheet resistivities of 1.5-2 Ω/square, n+ and p+ polysilicon/TaSi2gate structures, Threshold voltages of 0.4 V and 1.5 µm separation between active to tub-edge regions. Diode characteristics of the CoSi2/n+ and CoSi2/P+ are determined to be as good as non-silicided silicon junctions. Maintaining the proper doping for the connected n+ and p+ polysilicon/silicide gates is demonstrated. Ring oscillator delays of 110 ps at 3.5 V are observed for devices with 0.5 µm channel lengths. The ring oscillator circuits are still operational at power supply voltages of 1.0 V due to the low threshold voltage of the transistors.

Process limitation and device design tradeoffs of self-aligned TiSi/sub 2/ junction formation in submicrometer CMOS devices

Submicrometer CMOS transistors require shallow junctions to minimize punchthrough and short-channel effects. Salicide technology is a very attractive metallization scheme to solve many CMOS scaling problems. However, to achieve a shallow junction with a salicide structure requires careful optimization for device design tradeoffs. Several proposed techniques to form shallow titanium silicide junctions are critically examined. Boron, BF/sub 2/, arsenic, and phosphorus dopants were used to study the process parameters for low-leakage TiSi/sub 2/ p/sup +//n and n/sup +//p junctions in submicrometer CMOS applications. It is concluded that the dopant drive-out (DDO) from the TiSi/sub 2/ layer to form a shallow junction scheme is not an efficient method for titanium salicide structure; poor device performance and unacceptably leaky junctions are obtained by this scheme. The conventional post junction salicide (PJS) scheme can produce shallow n/sup +//p and p/sup +//n junctions with junction depths of 0.12 to 0.20 mu m below the TiSi/sub 2/. Deep submicrometer CMOS devices with channel length of 0.40 to 0.45 mu m can be fabricated with such junctions. >

Ultra-fast (0.5- mu m) CMOS circuits in fully depleted SOI films

CMOS dual-modulus, divide by 128/129, prescaler circuits were built in thin Si films on SIMOX (separation by implantation of oxygen) wafers. They operated at 6.2 GHz, which is 50% faster than control circuits built in bulk Si. Detailed electrical characterization of individual n- and p-channel transistors was performed. The capacitances for the n and p diodes were also measured. Using these data in circuit simulations, it was determined that the gain in speed was primarily due to the decrease in the parasitic capacitances, in particular that of the source/drain junctions. Also measured were the ring-oscillator delay times, with a minimum delay per stage of 34 ps. >

Ultra-high speed CMOS circuits in thin SIMOX films

CMOS dual-modulus prescaler circuits were built in very thin SIMOX films. They operate at 6.2 GHz, the highest speed ever reported for a digital CMOS circuit and 50% faster than the control circuits built in bulk Si. The high speed is obtained by taking advantage of the intrinsic properties of the SOI (silicon-on-insulator) structure combined with the symmetric CMOS technology that simultaneously optimizes the characteristics of both the p- and n-channel transistors.<<ETX>>

Fluorine effect on boron diffusion of p/sup +/ gate devices (MOSFETs)

A device characteristics instability in MOSFETs associated with fluorine incorporation in the p/sup +/-gate fabrication is reported. MOSFETs with BF/sub 2/ or boron-implanted polysilicon gates are fabricated identically except at gate implantation. A substantial shift and fluctuation in the threshold voltages of MOSFETs with BF/sub 2/-implanted gates are observed, even under moderate annealing conditions, while the boron-implanted gate devices still exhibits normal characteristics. The threshold voltage is found to shift more positively, and the subthreshold swing shifted to a large value as the fluorine concentration increased in the gate. The physical causes accounting for the threshold voltage shift are identified to be the fluorine-enhanced boron penetration and/or negative charge generation.<<ETX>>

W-polycide dual-gate structure for sub-1/4 micron low-voltage CMOS technology

We describe a simple, low cost process, suitable for fabrication of low-voltage sub-1/4 micron CMOS devices, utilizing W-polycide dual-gate structure. The novel feature of this process is a low gate stack profile (150-200 nm), made possible by implanting dopants directly into tungsten silicide. The threshold voltage shifts due to lateral dopant diffusion between P- and NMOS devices with connected gates are minimized (<30 mV) by combining thermal treatments with selective nitrogen gate co-implant to control dopant activation and diffusion. Both P- and NMOS devices have excellent I/sub on//I/sub off/ characteristics, low leakage currents, good short channel behavior and low gate sheet resistance of 8-10 /spl Omega///spl square/.

Integration of poly buffered LOCOS and gate processing for submicrometer isolation technique

Summary form only given. A modified poly buffered LOCOS (PBL) process is described which simplifies processing and provides advantages over conventional PBL and LOCOS processes. The use of a poly buffer between the pad oxide and the nitride layer offers the opportunity of integrating the poly gate deposition and the field isolating process and overcomes the processing difficulties of the conventional PBL while maintaining the advantage of a narrow spacing between active areas (THINOX). The process sequence of the conventional PBL and the integrated PBL (IPBL) process are summarized. >

Self-aligned silicided inverse-T gate LDD devices for sub-half micron CMOS technology

A nitride-sealed L-shaped Si spacer technique is used to form inverse-T gate sub-half micron N- and P-LDD (lightly doped drain) device structures with self-aligned Ti silicided gate and source-drain. The advantage of the L-shaped Si spacer N-LDD devices over the L-shaped nitride spacer devices is to extend the gate electrode so that it fully overlaps the N/sup +/ S/D region, which provides (1) higher current drive due to a reduction of series resistance with an increased carrier concentration at the LDD region and (2) less degradation during hot carrier aging due to a reduction of maximum lateral electric field and greater tolerance to higher trapped charges.<<ETX>>

RTA processing of W-polycide dual-gate sub-micron structures for low-voltage CMOS technology

Deep submicron CMOS technology for low-power, low-voltage applications requires the use of symmetric n{sup +}/p{sup +} poly gate structures. This requirement introduces a number of processing challenges, involving fundamental issues of atomic diffusion over distances of 1{angstrom} to {approximately} 30 {micro}m. Two of the critical issues are dopant cross-diffusion between P- and NMOS devices with connected gates, resulting in large threshold voltage shifts, and boron penetration through the gate oxide. The authors show that in devices with W-polycide dual-gate structure most of these problems can be alleviated by using rapid thermal annealing, RTA, in combination with a few additional, simple processing steps (e.g., low-temperature recrystallization of a-Si layer and selective nitrogen co-implants). The RTA step, in particular, ensures that the boron activation in the p{sup +} poly-Si remains high and negates any effects of arsenic cross-diffusion. CMOS devices with properly processed gates have low gate stack profiles, small threshold voltage shifts (< 30 mV), and excellent device characteristics.

Gate oxide thinning at the active device/FOX boundary in submicrometer PBL isolation

The impact of several poly buffer LOCOS processing parameters on the integrity and defect density (yield) of the gate oxide has been investigated by correlating electrical and structural studies. We found that a thin PBL pad-oxide, in general, gives rise to higher defect density. In addition, it results in a sharp active device/field oxide (FOX) boundary which, by the process of screen oxide growth and etch-back and FOX pull-back, creates a step in the Si in the birds beak region. TEM studies revealed gate oxide thinning by as much as 30% over this step, explaining the early gate oxide breakdown at the active device/FOX region.