S. Martoiu

A pixel front-end ASIC in 0.13 μm CMOS for the NA62 experiment with on pixel 100 ps Time-to-Digital Converter

The paper describes the design of a front-end chip for hybrid pixel detectors optimized for good timing resolution (200 ps rms) and high event rate (150 kHz per pixel). Each channel consists of a fast transimpedance amplifier with 5 ns peaking time, a constant fraction discriminator (CFD), and a Time-to-Digital Converter (TDC). In order to cope with the rate requirement, a multi-event buffering scheme employing both analog and digital pipelines is implemented in each cell. This development is part of the R&D activity for the silicon tracker of the NA62 experiment at CERN. The architecture of the chip and the design of the critical building blocks are discussed in the paper.

Experimental results from a pixel front-end for the NA62 experiment with on pixel constant fraction discriminator and 100 ps Time to Digital Converter

The paper presents test results of a front-end ASIC developed for fast timing applications with silicon pixel detectors. Implemented in a 0.13 μm CMOS process, the prototype integrates 107 read-out cells. In an area of 300 μm × 300 μm each cell incorporates a fast transimpedance amplifier with 3 ns peaking time, a Constant Fraction Discriminator (CFD) and a Time to Digital Converter (TDC). The analog front-end is optimized for signals from 1 fC to 10 fC and dissipates lmW from a 1.2 V supply. Electrical tests of the key building blocks and system level aspects are discussed in the paper.

Development of the ASICs for the NA62 pixel gigatracker

We present the ASIC development for the readout electronics of the Gigatracker pixel detector of NA62. Specifications of this detector are challenging in terms of timing precision with a hit time stamp accuracy of 100 ps and a peak hit rate of 50 Mhits/cm/s. A timing precision and hit rate are more than one order of magnitude faster than pixel LHC readout ASIC. The research for pixel cell design and the readout architectures are following two approaches, which are presented and discussed in this paper. Presently demonstrator prototypes are under development and SPICE simulation results of the frontend, the readout strategy and and the pixelcolumn are also presented and discussed.

Pixel read-out architectures for the NA62 gigatracker

Beam particles in NA62 experiment are measured with a Si-pixel sensor having a size of 300 μm x 300 μm and a time resolution of 150 ps (rms). To meet the timing requirement an adequate strategy to compensate the discriminator time-walk must be implemented and an R&D effort investigating two different options is ongoing. In this presentation we describe the two different approaches. One is based on the use of a constant-fraction discriminator followed by an on-pixel TDC. The other one is based on the use of a Time-over-Threshold circuit followed by a TDC shared by a group of pixels. The global architectures of both the front-end ASIC will be discussed. I. THE GIGATRACKER SYSTEM The aim of the proposed NA62 experiment at the CERN SPS is to study the very rare decay of the charged K meson into a pion and neutrino-antineutrino pair. One of the key components of NA62 will be the GigaTracker, which consists of three matrices of Si-pixel stations, each covering a sensitive area of 60 mm x 27 mm. Each pixel is 300 μm x 300 μm [1]. The GigaTracker is designed to measure the beam particle trajectory with a space resolution of 100 μm (rms) and a timing accuracy of 150 ps (rms). In order to reconstruct the momentum of the beam particles a system of four dipoles, A1...A4 in Fig.1, provides the momentum selection followed by the beam recombination. The timing resolution of 150 ps (rms) is an unusual requirement for a traditional pixel detector and none of the existing systems has such a capability. Other challenging aspects are due to the high radiation operational environment and the very low material budget restraint (0.5% X0 per station, sensor thickness 200 μm, read-out chip thickness 150 μm). Figure 1: GigaTracker system Each silicon sensor will be read-out by 10 front-end ASICs, with 45x40 read-out cells each. The 10 read-out chips will be bump-bonded to the pixels, so only one side of the chip will be used for external connections (wire bonding pads in Fig. 2). Figure 2: Sensor and read-out chips The particle rate, which is higher in the central part of the sensor, is estimated to be ~1.5 MHz/mm maximum, which corresponds to 130 MHz per chip and 140 kHz per

An ultra fast 100 ps, 100 µm 3D-pixel imager

We present the development of a charged particle pixel array imager operating in single hit detection mode. This challenging imaging device called GigaTracker (GTK) developed for the CERN NA62 experiment is intended to measure the position and arrival time of a pion/kaon beam with an intensity of 108*cm-2*s-1. Each particle hit is detected in position with a precision of ~100 &mgr;m and in time with a precision of 100 ps (rmsc). The readout pixel ASIC circuit in 130 nm CMOS technology comprise an array of 1800 pixels of 300 x 300 &mgr;m2. It is connected via bump bonding to an ultra fast solid state pixel sensor array matching the same pixel pattern. The performance of high rate and high timing precision together with an extreme sensitivity of the pixel channel discriminating input signals with a charge as low as 1 fC (6000 electrons) are very demanding; two imaging readout architectures are presented, one with on pixel analogue based time-to-digital-converter (TDC), the other one with digital based TDC placed at the end of each column. The design of two pixel discriminators, a constant fraction discriminator and a time-over-threshold discriminator with time walk correction technique will be discussed. The design challenges of two architectures will be also discussed. Due to the high particle intensity, a huge data flow has to be handled. Hereby only data of pixels, which actually have been hit are buffered on chip and automatically transferred off the chip. The data rate per chip is 4 Gbit/s. We present circuit design challenges and SPICE simulations of both approaches.

READOUT ELECTRONICS OF THE NA62 GIGATRACKER SYSTEM

A crucial detector of the NA62 experiment is the beam spectrometer named Gigatracker. It consists of three stations of hybrid silicon pixels sensors with 150 ps (rms) of time resolution and 100 μm (rms) of space resolution. In addition the system operates under a high radiation environment and a high density of particles (up to 1.5 MHz/mm in the centre and 0.8 1 GHz in total). To meet these requirements the readout electronics must compensate the discriminators time-walk and the dead time should be below 1%. In order to evaluate the best solution, two readout chips have been developed. One is based on the constant-fraction discriminator technique and the other one is based on the use of a time-over-threshold circuit. The global architectures of both the front-end ASIC will be discussed.