S. Mittal

Association of Tuberculous Endometritis with Infertility and Other Gynecological Complaints of Women in India

ABSTRACT Endometrial biopsy samples derived from 393 patients with assorted gynecological complaints were investigated for mycobacterial infection. By employment of four different techniques, mycobacterial pathogens were detected irrespective of the nature/type of clinical complaint. Mycobacterium tuberculosis was the predominant pathogen detected among the samples investigated.

Epitaxially Defined FinFET: Variability Resistant and High-Performance Technology

FinFET technology is prone to suffer from line edge roughness (LER)-based VT variation with scaling. It also lacks a simple implementation of multiple VT technology needed for power management. To address these challenges, in this paper we present an epitaxially defined FinFET (EDFinFET) as an alternate to FinFET architecture for nodes 15 nm and beyond. We show by statistical simulations that EDFinFET reduces overall VT variability with an 80% reduction in LER-based variability in comparison with FinFETs. We present dynamic threshold MOS (DTMOS) configuration of EDFinFET using the available body terminal to individual transistors. The DTMOS configuration reduces LER-based variability by 90% and overall variability by 59%. It also has excellent subthreshold slope (SS) and gives 43% higher ION compared with FinFETs. Meanwhile, EDFinFET shows poorer SS and lower ION than FinFET due to single gate control. However, it is capable of multiple VT, which leads to circuit level power optimization.

An Analytical Model to Estimate FinFET’s

Line-edge roughness induced fin-edge roughness (FER) is the primary source of VT variation in FinFETs. Conventionally, stochastic simulations are performed to predict the device variability due to FER for a technology, which are computationally expensive. An analytical formulation to predict variability due to FER enables understanding of the effect of input parameters as well as provides quantitative results at fractional computational costs. In this paper, we develop and present an analytical model to estimate saturation VT(VT-sat) variability due to FER. The model is capable of capturing the VT variability dependence on device parameters (LG and Wfin) and variability parameters (correlation length Λ and standard deviation Δ) accurately. The entire VT-sat distribution obtained by the model is also presented and compared against the VT-sat distribution of stochastic simulations to show that the model captures the distribution effectively. We show that not only σ VT but even μVT is affected by variability parameters. Hence, such modeling is critical to defining nominal FinFET structure (LG and Wfin), which is affected by variability (Λ and Δ) especially for scaled FinFETs, where quantum-confinement effects are enhanced.

V_{T}

Device variability has become a major concern for CMOS technology [1]. Various sources of variability include Random Dopant Fluctuation (RDF), Gate Edge Roughness (GER) and Line Edge Roughness (LER) [2]. The introduction of FinFETs at 22nm node has two issues. Firstly, the effect of RDF is considerably reduced due to undoped fins [3]. But the aggressive fin width (Wfin) requirement (~Lg/3 [4]) to reduce short channel effect aggravates the electrical impact of LER and makes it greatest contributor to patterning induced variability [2]. Moreover, the edge roughness does not scale with technology and remains independent of the type of lithography used [5]. Secondly, multiple threshold voltage (VT) is achieved in planar technology by various patterned implant steps, which is unavailable for FinFET technology as the fin is undoped. Multiple VT transistor technology is essential for power vs. performance optimization by circuit designers [6]. In this work, we propose an alternative to conventional FinFET structure which can (a) reduce overall variability by 4× reduction in sensitivity to LER and (b) enable multiple VT by applying body bias dynamically without any costly patterned implant steps.

Distribution Due to Fin-Edge Roughness

Band to band tunneling (BTBT) is a major challenge in Ge FinFETs due to its smaller band gap. Narrow fin widths reduce BTBT due to quantum confinement (QC). However, Line Edge Roughness (LER) on narrower fins causes large VT variability. Previously, we have proposed an architecture named Epitaxially Defined (ED) FinFET to reduce VT variability due to LER wherein channel depletion is defined by low doped highly uniform epitaxy (thus named Epi Defined FinFET) (epi-thickness non uniformity<;2%) over a thick highly doped Si fin instead of lithography based patterning subject to LER (non-uniformity<;50% i.e. 2nm LER on a 4nm fin). In the present work, we propose integration of Ge into EDFinFET architecture in which Ge (or SiGe) is grown on top of Si fin. Proposed structure shows 10× reduction in LER based VT variability in comparison to FinFETs. Valence band QC in gate oxide/Ge/Si stack is used to control BTBT. Biaxial stress in thin Ge epitaxially grown on Si results in 27% higher ION. Thin Ge film required is lower than critical defect free thickness of Ge epitaxy on Si. Hence defect free Ge integration into FinFET architecture in enabled. We also show that EDFinFET can enable multiple VT just by the application of a bias at the body terminal.

Epitaxialy defined (ED) FinFET: to reduce V T variability and enable multiple V T

FinFETs electrostatics depends largely on the fin width (W_FIN). Herein we demonstrate that an optimal W_FIN exists at which the variability is minimized. We present in this work that at higher W_FIN, degraded electrostatics causes both gate edge roughness (GER) and line edge roughness (LER) based variability to degrade. On the other hand, at lower W_FIN, LER induced quantum confinement (QC) strongly degrades variability [1]. Thus an optimized W_FIN/L_G ratio for different technology nodes based on variability is obtained, which is nearly 0.33. The obtained ratio is in the range of electrostatics thumb-rule for W_FIN/L_G (=0.25-0.5) [2]. Also, at constant LER/GER 3σ (=2 nm), V_T variability increases strongly with scaling. To enable constant V_T variability, the LER/GER 3σ (in nm) patterning variability requirement is also presented.

Epi defined (ED) FinFET: An alternate device architecture for high mobility Ge channel integration in PMOSFET

Several emerging devices have been proposed to continue the CMOS scaling. To assess scalability, device and circuit variability estimation is essential. Variability in static noise margin (SNM) in a 6T-SRAM cell is a key metric to assess the impact of device-level variability at the circuit level. This is usually enabled by SPICE simulations, which needs device compact models. However, the development of a SPICE model usually takes a significant amount of time (e.g., a few years). In this paper, we present a method to enable the evaluation of the SRAM cell SNM variability based on the ID-VG distribution at various VDS values of a device (obtained either experimentally or from TCAD), which can enable this assessment before the development of a SPICE model. Thus, it enhances the accuracy by being able to capture the effects of full ID-VG distribution rather than just VT distribution. The method is validated against HSPICE for a variety of SRAM parameters, such as Read, Hold, and Write SNM, write trip point, and read current (IREAD) to show excellent accuracy. The method also shows a 30× improvement in computational efficiency over mixed-mode TCAD-based stochastic SRAM simulation. A case study for the comparison of recently proposed low-variability EDFinFET with FinFET is presented using this method.

FinFET scaling rule based On variability considerations

Band to band tunneling (BTBT) is a major challenge in Ge FinFETs due to its smaller band gap. Reduction in BTBT by quantum-confinement (QC) based increase in band-gap requires narrow Wfin. However, Line Edge Roughness (LER) on narrow fins causes large VT variability. Improved fin-width process e.g. SADP [1], ALE [2] have been proposed to reduce LER. Alternatively, variability resistant transistor design has been recently proposed with thin Ge on Si highly retrograde doped fins by our group [3], which also provides multiple VT capability - a major challenge in FinFETs. However, this has 2 challenges - (i) thickness limitation of <; 2nm of defect-free Ge on Si and (ii) RDF in the retrograde doped fins. In this study, we propose a dual-gate structure like FinFET by epitaxially growing undoped Ge /rare earth oxide (e.g. Gd2O3) [4] stack on highly doped Si fins. By statistical simulations, we show that this structure can reduce LER based variability by more than 90% in comparison to FinFETs at a similar performance. RDF is negligible due to the undoped Ge channel. Thicker (>2nm) defect-free Ge can be grown epitaxially on Gd2O3 [4]. We show the multi-VT capability enabled by independent back-gate biasing, and hence provides a significant advantage over FinFETs. Experimental data from MOSCAP with epi Gd2O3 as gate dielectric (~ 4.5 nm) show lower leakage currents than LSTP specification.

Statistical Variability Analysis of SRAM Cell for Emerging Transistor Technologies

Abstract Estimation of threshold voltage V T variability for NWFETs has been computationally expensive due to lack of analytical models. Variability estimation of NWFET is essential to design the next generation logic circuits. Compared to any other process induced variabilities, Metal Gate Granularity (MGG) is of paramount importance due to its large impact on V T variability. Here, an analytical model is proposed to estimate V T variability caused by MGG. We extend our earlier FinFET based MGG model to a cylindrical NWFET by satisfying three additional requirements. First, the gate dielectric layer is replaced by Silicon of electro-statically equivalent thickness using long cylinder approximation; Second, metal grains in NWFETs satisfy periodic boundary condition in azimuthal direction; Third, electrostatics is analytically solved in cylindrical polar coordinates with gate boundary condition defined by MGG. We show that quantum effects only shift the mean of the V T distribution without significant impact on the variability estimated by our electrostatics-based model. The V T distribution estimated by our model matches TCAD simulations. The model quantitatively captures grain size dependence with σ ( V T ) with excellent accuracy ( 6 % error) compared to stochastic 3D TCAD simulations, which is a significant improvement over the state-of- the-art model with fails to produce even a qualitative agreement. The proposed model is 63 × faster compared to commercial TCAD simulations.

Epitaxial rare earth oxide (EOx) FinFET: A variability-resistant Ge FinFET architecture with multi V T

Metal gate granularity (MGG) induced threshold voltage (Vt) variability is a critical process random variations for sub-20nm transistors [1]. It has been studied using either by stochastic TCAD simulations[2] or by analytical modeling of probability distribution[3]. This analytical modeling is based on the approach of finding an effective WF. This is a weighted average on the area of WFs of all the grains. The probability distribution of this effective WF is expected to be correlated with distribution of Vt. The problem with this approach is that positional randomness is ignored and the results depend only on the fraction of the area covered by a particular grain. Hence a physics based analytical model is attractive to address this issue. The electrostatics of NWFETs has been well explained and studied to model Vt and subthreshold slope (SS) are found [4] and [5]. The objective of this work is to develop an analytical model to estimate the metal gate granularity (MGG) induced Vt variability in Silicon nanowire FETs (NWFETs) using analytical solution of equilibrium electrostatics.