S. Ogawa

Interface microstructure of titanium thin‐film/silicon single‐crystal substrate correlated with electrical barrier heights

The titanium (Ti)/single‐crystal silicon (Si) interface has been examined by cross‐section high‐resolution transmission electron microscopy (HRTEM) combined for the first time with 2‐nm‐diam probe, energy‐dispersive spectrometry. HRTEM shows that thin Ti‐Si alloy formation always occurs at the interfaces, even in the as‐deposited state. The thickness of the reacted alloy depends on the crystallinity of the Si surface, but does not depend on impurities or doping level. Crystallization of the Ti‐Si alloy depends on the annealing temperature; it remains in the amorphous phase after annealing at temperatures lower than 430u2009°C, and the C49 TiSi2 crystal phase was observed as the first crystalline phase after annealing at 460–625u2009°C. The composition of the Ti‐Si alloy at the Si interface is close to TiSi2, and it remains amorphous with variable composition across the alloy. It seems that the electrical barrier height is determined by the degree of crystallinity of TiSi2 at the Si interface. The barrier height f...

Dependence of thermal stability of the titanium silicide/silicon structure on impurities

The effect of impurity on the thermal stability of titanium silicide (TiSi2)/single‐crystal silicon (Si) structures has been studied. It is found that nitrogen and oxygen in the TiSi2 film significantly influence the morphological changes of a TiSi2/Si structure during high‐temperature annealing at 1100u2009°C for 2–20 s. Nitrogen impurity improves the thermal stability of the TiSi2/Si structure, whereas oxygen degrades it.

Fabrication technologies for dual 4-kbit stacked SRAM

The process technologies for realizing a 3-D LSI are reported with emphasizing the high quality laser recrystallization and the thermally stable interconnects. A homogeneous recrystallization of the silicon island array was achieved all over a wafer by the dual laser beam recrystallization method (DLB), in which the 2-dimensional energy distribution of the laser beam was precisely controlled. Thermally stable interconnects in the 1st layer were realized by W wiring and stoichiometry controlled W/WSi/Si contact structure. By these key technologies, the 8-kbit CMOS SRAM with two-active layers has been fabricated. It was confirmed that these technologies were available to fabricate the 3-D LSI.

Multilayer CMOS device fabricated on laser recrystallized silicon islands

Multilayer CMOS devices were fabricated by a laser recrystallization technology. The single crystalline silicon islands embedded in an insulator on the top of MOS IC were studied. To minimize the thermal influence on a lower IC during the fabrication process, a CVD-SiO2was used as a retaining wall of silicon islands instead of a LOCOS. In addition, a planarized heat sink (PHS) polysilicon layer was employed to eliminate the impediment to a grain growth at the steps due to a lower IC. The single crystalline silicon islands were successfully obtained. The field effect mobility of NMOS transistors fabricated on single-crystallied silicon islands was calculated as about 400 cm2/V.sec, 490cm2/V.sec. The 10 bit CMOS shift register fabricated just on a lower IC was successfully operated at VDD=6.5 V, fCLK= 1 MHz. The 4 bit CMOS shift register, stacking PMOS on NMOS was also successfully operated.

Reliable submicron vias using aluminum alloy high temperature sputter filling

The authors have developed a reliable submicron via formation technology using Al-Si-Cu high temperature sputter filling with a thin Ti underlayer. Complete filling of a 0.5 mu m diameter via hole with an aspect ratio of 1.6 was achieved. Crystallinity of the aluminum in the via was single crystalline

Time‐dependent p‐n junction characteristics underneath TiN/Ti contact metal

Time‐dependent p‐n junction characteristics (junction depth: xj∼0.2 μm) underneath TiN/Ti contact metal have been determined in terms of contact interface crystallinity. Reverse bias (≥6.0 V) soft‐breakdown characteristics result in a leakage current increase during reverse bias and temperature aging stress. It has been elucidated that this degradation is dependent on the crystallinity of Ti‐Si interdiffused layers at the contact interface and the p‐n junction polarity. The degradation is observed only in amorphous Ti‐Si contacted n+‐p junctions. Nevertheless, in amorphous Ti‐Si contacted p+‐n junctions and crystalline TiSi2 contacted n+‐p and p+‐n junctions, the degradation does not appear. In the case of the amorphous Ti‐Si contacted n+‐p junction, it is concluded that the time‐dependent degradation is caused by diffusion of positively ionized Ti enhanced by the applied electric field.

A novel Al-Sc (scandium) alloy for future LSI interconnection

A new aluminum alloy, Al-Sc (scandium), has been studied in comparison with a conventional Al-Si-Cu alloy for future LSI interconnection. It has been found that Sc addition into Al completely suppressed a failure caused by a stress-induced migration phenomenon (SM) in submicron lines and hillock generation, while showing superior electromigration (EM) performance to conventional Cu addition. The new impurity, Sc, precipitates and presumably acts as a sink site for vacancies, which are the origin of the degradation in reliability by SM and EM.<<ETX>>

Nondestructive depth profile measurement of a Co/Ti bilayer using refracted x‐ray fluorescence

The depth profile of a Co (300 A)/Ti (50 A) bilayer on Si(100) is studied by nondestructive refracted x‐ray fluorescence before and after annealing. Following annealing, the angular distribution of the x‐ray fluorescence indicates an inversion of the Co and Ti layers and the formation of CoSi2. These were confirmed by cross‐section transmission electron microscopy and x‐ray nanoprobe measurements. This success suggests that refracted x‐ray fluorescence, which can be used as an in situ probe, may be ideally suited for analysis of thin‐film reactions and interdiffusion.

Structure and electrical properties of interfaces between silicon films and n+ silicon crystals

We have studied the morphology and electrical characteristics of the interfaces between silicon‐implanted, low‐pressure chemical‐vapor‐deposited (LPCVD) silicon films with an n+ single‐crystal silicon substrate. Using high‐resolution transmission electron microscopy, it is shown that the silicon implant causes a ‘‘balling up’’ of the native oxide layer at the interface and epitaxial growth occurs in the LPCVD silicon film even after rapid thermal annealing at only 940u2009u2009°C for 30 s. This morphological change results in a realization of a low‐ohmic‐resistivity LPCVD silicon/ n+ single‐crystal silicon contact even at a sub‐half‐μm size, although the unimplanted contact becomes nonohmic. The leakage current for the implanted contact is as low as that for the unimplanted one in shallow junctions.

A highly reliable sub-half-micron via and interconnect technology using Al alloy high-temperature sputter filling

A technology using Al-Si-Cu alloy high-temperature sputter filling and a thin Ti underlayer to prevent Si from precipitating is discussed. Complete filling of a 0.15- mu m-diameter via with aspect ratio of 4.5 has been achieved. The resistance of the 0.3- mu m sputter filled via was 0.71 Omega . This is about one order of magnitude lower than that for a conventional via. The electromigration resistance of the 0.3- mu m filled via was found to be four orders of magnitude greater than that of the conventional vias. Superior stress-induced migration resistance of 0.5- mu m wide lines was confirmed.<<ETX>>