S.W.R. Lee

Characterization and analysis on the solder ball shear testing conditions

This paper presents both experimental investigation and computational analysis on the solder ball shear testing conditions for ball grid array (BGA) packages. The experimental data of solder ball shear tests indicate that the ram height and the shear speed have substantial effects on the solder ball shear strength. The general trend shows that lower ram height and faster shear speed can result in higher ball shear strength. A two-dimensional finite element model is established to simulate the solder ball shear tests. The results in terms of load-displacement curve from computational analysis are in good agreement with the experimental data. Based on the computational stress analysis, an effort is made to interpret the failure mode of solder balls subject to the ball shear test.

Brittle Failure Mechanism of SnAgCu and SnPb Solder Balls during High Speed Ball Shear and Cold Ball Pull Tests

This study investigated brittle solder joint failure mechanisms during high-speed solder ball shear and pull testing. BGA package samples with different solder alloys (Sn4.0%Ag0.5%Cu and Sn37%Pb) were fabricated and a series of solder ball shear and pull tests were conducted at various testing speeds. The ball shear test speeds ranged from 10 mm/s to 3000 mm/s, while the ball pull test speeds ranged from 5 mm/s to 500 mm/s. Following high-speed shear/pull testing, the brittle fracture surfaces of the solder balls and corresponding pad were inspected using SEM/EDX. The results describe an increased incidence of brittle interfacial fracture for SnAgCu solder compared to SnPb solder. Microstructure analysis of brittle solder joint fracture surfaces appears an effective method to aid correlation between board level drop test and high-speed solder ball shear/pull tests.

Effect of Thermal Aging on High Speed Ball Shear and Pull Tests of SnAgCu Lead-free Solder Balls

Solder joint reliability concerns are increasing exponentially with the continuous push for device miniaturization, and the expanded use in portable electronic products. In order to predict the solder joint reliability under drop conditions, it is important to increase the testing speed of package level test methods, such as high-speed solder ball shear and pull. Traditional ball shear and pull tests are not considered suitable for evaluation of joint reliability under drop loading, since the applied test speeds, usually lower than 5 mm/s, are well below the impact velocity applied to the solder joint in a drop test. Recently, high-speed shear and pull test equipment (Dage 4000HS) with testing speeds beyond 1,000 mm/s has become available. The present study continues the efforts reported recently and investigates the effect of thermal aging on the attachment strength and fracture energy of SnAgCu lead-free solder balls during high speed ball shear/pull tests. The ball shear test speeds ranged from 100 mm/s to 1,000 mm/s, while the ball pull test speeds ranged from 5 mm/s to 100 mm/s. The test specimens were aged at 125degC or 150degC for durations of 100, 300 and 500 hrs, with some additional samples exposed up to 1,000 hrs. Correlations were established between solder joint fracture force/energy and IMC thickness, and between fracture energy and failure mode.

Comparison of Joint Strength and Fracture Energy of Lead-free Solder Balls in High Speed Ball Shear/Pull Tests and their Correlation with Board Level Drop Test

A comprehensive solder joint reliability study was conducted using both high-speed solder ball shear/pull and board level drop testing (BLDT). The samples were divided into groups which were subject to various periods of thermal aging (125degC, up to 500 hours) in order to accelerate the formation of intermetallic compound (IMC) in the solder joints. The ball shear tests ranged from 10 mm/s to 3,000 mm/s while the ball pull tests ranged from 5 mm/s to 500 mm/s. A total of 6 unique package constructions were evaluated, ranging from a 316 PBGA (27 mm, sq) to a 2,395 CBGA (51 mm, sq). The samples used SAC lead-free solder balls and a variety of pad surface finishes. Detailed failure analyses were performed to identify the failed solder joints and corresponding failure modes. The failure modes and loading speeds of ball shear and ball pull tests were cross-referenced with the mechanical drop tests for comparison. Correlation models were established relating drops-to-failure with both solder ball fracture force and energy.

Three-dimensional packaging for multi-chip module with through-the-silicon via hole

This paper presents an innovative package design for multi-chip modules. The developed package has a flip-chip-on-chip structure. Four memory chips (DRAM for demonstration) are assembled on a silicon chip carrier with eutectic Sn-Pb solder joints. The I/Os of memory chips are fanned-in on the silicon chip carrier to form an area array with larger solder balls. An optional through-the-silicon via hole is made at the center of the chip carrier for underfill dispensing, if required. The whole multi-chip module is mounted on the printed circuit board by the standard surface mount reflow process. After the board level assembly, all specimens are inspected by X-ray and divided into two groups. One group is encapsulated with underfill and the other group is not. For those packages with encapsulation, the underfill is dispensed through the aforementioned via hole to encapsulate the solder joints and memory chips. Subsequently, scanning acoustic microscopy is performed to inspect the quality of underfill. Afterwards, all specimens are subject to the accelerated temperature cycling (ATC) test. During the ATC test, the electrical resistance of those packages is monitored. The experimental results show that the packages without underfill encapsulation may fail in less than 100 thermal cycles while those with underfill can last for more than 1,000 cycles. From the dye ink analysis and the cross-section inspection, it is identified that the packages without underfill have failure in the silicon chip carrier, right under the pads of large solder balls. The ATC test of packages with underfill encapsulation is still ongoing (no observable failure recorded up to 1,200 cycles). With this innovative package design, low profile and high density multi-chip modules can be implemented. Due to the unique package structure and underfill encapsulation, it is believed that good board level reliability can be achieved.

Novel sequential electro-chemical and thermo-mechanical simulation methodology for annular through-silicon-via (TSV) design

Through-silicon-via (TSV) becomes an emerging interconnection technology with various TSV structures, among which the annular-TSV demonstrates great application potentials because of its simple manufacturing processes and low cost. Due to the mismatch of coefficient of thermal expansion (CTE) among various materials leading to various quality and reliability issues, it is necessary to develop a novel modeling/simulation approach to help with optimizing annular-TSV structures and process parameters because the plated-Cu uniformity highly depends on Cu-plating solution, plating process and via location. Therefore, a novel sequential electro-chemical and thermo-mechanical simulation methodology was developed with simulation procedures as the electro-chemical analyses to simulate Cu-plating process, followed by the thermo-mechanical analyses (from wafer-level model, chip-level model to via-level model) to simulate key TSV insulation/plating processes using global-local and death-birth simulation methods. Based on the novel simulation methodology, this work studied the variations of plated-Cu thickness and found the stress of annular-TSVs near wafer edge was larger than that at wafer center by 16%~18% due to the Cu-plating non-uniformity. The stress of annular-TSVs would increase by 10%~31% and by 9%~27% if reducing the Cu seed thickness from 2um to 0.5um and reducing the via pitch from 300um to 150um, respectively.

Optimization of epoxy flow for passive alignment of optical fiber arrays

Alignment is very critical in optoelectronic packaging and slightly offset in any direction will affect the performance of the whole system. Optical fiber is one of the most commonly used as light transmitting medium. It is usually coupled with different components such as light source, photo-detector and waveguides. As the core diameter of glass optical fiber is usually small, active alignment is used to ensure the alignment. However, the equipment cost of active alignment is very high and the process time is long. This makes the whole alignment process very expensive and ineffective as stated in M. F. Dautartas et al. (2002) and M. W. Beranek et al. (2000). Recently, passive alignment by utilizing precisely etched V-grooves is getting more common due to its low cost and short cycle time based in P. Karioja et al. (2000) and K. Yamauchi et al. (2000). During the passive alignment process, the optical fiber may be lifted up by the buoyancy of the epoxy and hence an extra covering plate is normally required to press the fibers against the wall of V-grooves. The extra plate may introduce several problems. In this paper, an innovative method of dispensing the epoxy is presented. This introduces the self-alignment capability to the conventional passive alignment method. Also by using the new method, the extra covering plate is not required. It is found that the amount of epoxy dispensed is critically in the process. Also the viscosity of the epoxy determines the flow and hence affects the results. In this paper, the effect of the volume and viscosity of epoxy is studied. From the experimental results, the modified passive alignment method is capable of aligning multiple fibers on fiber arrays up to 8 channels up to 1 micron.